| Residential College | false |
| Status | 已發表Published |
| A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC | |
Si-Seng Wong1 ; U-Fat Chio1; Yan Zhu1 ; Sai-Weng Sin1; Seng-Pan U1,2; R. P. Martins1,3
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| 2012 | |
| Conference Name | 34th Annual IEEE Custom Integrated Circuits Conference (CICC) |
| Source Publication | Proceedings of the IEEE 2012 Custom Integrated Circuits Conference
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| Conference Date | 9-12 Sept. 2012 |
| Conference Place | San Jose, CA, USA |
| Abstract | A 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC architecture is proposed, where the ADC's front-end is built with a 5b binary-search ADC, shared by two time-interleaved 6b SAR ADCs in the 2 -stage. The design prevents the use of opamp that causes large power dissipation. Besides, a process insensitive asynchronous logic is proposed to further reduce the delay of SA loop. The ADC was fabricated in 65nm CMOS and achieves 54.6dB SNDR at 170MS/s with only 2.3mW of power consumption, leading to a FoM of 30.8fJ/conversion-step. © 2012 IEEE. |
| Keyword | Analog-to-digital Converter (Adc) Binary-search Adc Time-interleaved Sar Adc Two-step Adc |
| DOI | 10.1109/CICC.2012.6330695 |
| URL | View the original |
| Indexed By | CPCI-S |
| Language | 英語English |
| WOS Research Area | Engineering |
| WOS Subject | Engineering, Electrical & Electronic |
| WOS ID | WOS:000310365600114 |
| Scopus ID | 2-s2.0-84869465536 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Conference paper |
| Collection | DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS |
| Affiliation | 1.State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China 2.Also with Synopsys - Chipidea Microelectronics (Macau) Limited 3.On leave from Instituto Superior Técnico (IST)/TU of Lisbon, Portugal |
| First Author Affilication | Faculty of Science and Technology |
| Recommended Citation GB/T 7714 | Si-Seng Wong,U-Fat Chio,Yan Zhu,et al. A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC[C], 2012. |
| APA | Si-Seng Wong., U-Fat Chio., Yan Zhu., Sai-Weng Sin., Seng-Pan U., & R. P. Martins (2012). A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. Proceedings of the IEEE 2012 Custom Integrated Circuits Conference. |
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