Residential College | false |
Status | 已發表Published |
A Quad-Output Hybrid Buck Converter with 8-Inductor Helping One Spot from All Quarters for Multi-Core XPUs | |
Mao, Xiangyu; Huang, Junwei; Tong, Zhiguo; Martins, Rui; Lu, Yan | |
2024-05 | |
Conference Name | 44th Annual IEEE Custom Integrated Circuits Conference, CICC 2024 |
Source Publication | Proceedings of 2024 IEEE Custom Integrated Circuits Conference |
Conference Date | 21-24 April 2024 |
Conference Place | Denver, Colorado |
Country | USA |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Abstract | Multi-core processors need per-core dynamic voltage and frequency scaling for higher system energy efficiency and have stringent fast load transient response requirement on the voltage regulators (VRs) for minimizing the voltage guard band [1]-[3]. Meanwhile, high v ^2R losses and IR drops on the power delivery networks limit the application of conventional buck converter. A multi-phase buck converter on board can only deliver accurate supply voltage to the package inputs. Then, the package parasitic inductance induces supply voltage droop and ringing on chip during load transients. The inductor-first or third-order buck converter [4], [5] places one small inductor each on the VIN and GND paths, providing an alternative way to implement multi-phase step-down conversion (Fig. 1 left). Then, the parasitic inductors on the VIN and GND paths will be part of the power inductors, and thus will not impact the transient performance of VDD. In addition, we can use in-package capacitors or deep-Trench capacitors, and place the inductors on the PCB back side, realizing a more compact solution. However, powering a high-performance processor still faces the fast load transient challenge. In some scenarios, the processor current can surge by several Amperes within a few ns, causing a large output droop. |
DOI | 10.1109/CICC60959.2024.10529095 |
URL | View the original |
Indexed By | CPCI-S |
Language | 英語English |
WOS Research Area | Engineering ; Telecommunications |
WOS Subject | Engineering, Electrical & Electronic ; Telecommunications |
WOS ID | WOS:001230023800134 |
Scopus ID | 2-s2.0-85193917660 |
Fulltext Access | |
Citation statistics | |
Document Type | Conference paper |
Collection | THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS |
Affiliation | University of Macau, Macao |
First Author Affilication | University of Macau |
Recommended Citation GB/T 7714 | Mao, Xiangyu,Huang, Junwei,Tong, Zhiguo,et al. A Quad-Output Hybrid Buck Converter with 8-Inductor Helping One Spot from All Quarters for Multi-Core XPUs[C]:Institute of Electrical and Electronics Engineers Inc., 2024. |
APA | Mao, Xiangyu., Huang, Junwei., Tong, Zhiguo., Martins, Rui., & Lu, Yan (2024). A Quad-Output Hybrid Buck Converter with 8-Inductor Helping One Spot from All Quarters for Multi-Core XPUs. Proceedings of 2024 IEEE Custom Integrated Circuits Conference. |
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