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High-speed robust level converter for ultra-low power 0.6-V LSIs to 3.3-V I/O Conference paper
Lei C.-T., U S.-P., Martins R.P.. High-speed robust level converter for ultra-low power 0.6-V LSIs to 3.3-V I/O[C], 2009, 396-399.
Authors:  Lei C.-T.;  U S.-P.;  Martins R.P.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/02/11
A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator Conference paper
Chan C.-H., Zhu Y., Chio U.-F., Sin S.-W., U S.P., Martins R.P.. A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator[C], 2009, 392-395.
Authors:  Chan C.-H.;  Zhu Y.;  Chio U.-F.;  Sin S.-W.;  U S.P.; et al.
Favorite | TC[WOS]:13 TC[Scopus]:19 | Submit date：2019/02/11
Dynamic Comparator  Offset Calibration  
Parasitic calibration by two-step ratio approaching techinque for split capacitor array SAR ADCs Conference paper
Wong S.-S., Zhu Y., Chan C.-H., Chio U.-F., Sin S.-W., U S.-P., Martins R.P.. Parasitic calibration by two-step ratio approaching techinque for split capacitor array SAR ADCs[C], 2009, 333-336.
Authors:  Wong S.-S.;  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.; et al.
Favorite | TC[WOS]:5 TC[Scopus]:9 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Offset Calibration  Parasitic Calibration  Split Capacitor Array  Sucessive Approximation Register (Sar)