This paper presents a high resolution and wide range offset calibration technique for high resolution comparators. The proposed calibration technique significant reduces the calibration capacitance from conventional 2 binary-scaled capacitors array to a small voltage-controlled capacitor. Furthermore, it utilizes inherent system clock to perform calibration and does not require extra clock phase. After proposed calibration, simulation result shows an offset of conventional dynamic comparators being reduced from 35mV to 350μV (one sigma) operating at 1GHz in 65nm CMOS technology with only 20μW power in calibration. ©2009 IEEE.