High-speed robust level converter for ultra-low power 0.6-V LSIs to 3.3-V I/O

doi:10.1109/SOCDC.2009.5423870

UM > INSTITUTE OF MICROELECTRONICS

Residential College	false
Status	已發表Published
	High-speed robust level converter for ultra-low power 0.6-V LSIs to 3.3-V I/O
	Lei C.-T.; U S.-P.; Martins R.P.
	2009-12-01
Conference Name	2009 International SoC Design Conference (ISOCC)
Source Publication	2009 International SoC Design Conference, ISOCC 2009
Pages	396-399
Conference Date	22-24 Nov. 2009
Conference Place	Busan, South Korea
Abstract	A new level converter aimed at ultra-low core voltage and wide range I/O voltage is designed using deep submicron process with standard MOS transistor without adding extra mask or process step. Simulation results demonstrate the performance improvement of the proposed level converter which can convert high-speed clock signals from 0.6-V to 3.3-V I/O interface within 0.5ns and maintain 50:53 of duty ratio. ©2009 IEEE.
DOI	10.1109/SOCDC.2009.5423870
URL	View the original
Indexed By	CPCI-S
Language	英語English
WOS Research Area	Computer Science ; Engineering
WOS Subject	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS ID	WOS:000290246700098
Scopus ID	2-s2.0-77951452800
Fulltext Access	View Full-Text via DOI View Full-Text via Web of Science View Full-Text via Scopus
Citation statistics
Document Type	Conference paper
Collection	INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation	Universidade de Macau
First Author Affilication	University of Macau
Recommended Citation GB/T 7714	Lei C.-T.,U S.-P.,Martins R.P.. High-speed robust level converter for ultra-low power 0.6-V LSIs to 3.3-V I/O[C], 2009, 396-399.
APA	Lei C.-T.., U S.-P.., & Martins R.P. (2009). High-speed robust level converter for ultra-low power 0.6-V LSIs to 3.3-V I/O. 2009 International SoC Design Conference, ISOCC 2009, 396-399.

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