A calibration technique is proposed to apply for split capacitor array of successive approximation register (SAR) ADC. This technique calibrates the parasitic effects of the split capacitor array by two-step ratio approaching technique, and achieves medium-to-high resolution. The calibration technique is designed and simulated under a 10-bit 100MS/s SAR ADC structure, with 15% to 25% of top plate parasitic capacitance. The simulation results show that the proposed technique can improve the THD from -41 dB to -59 dB at Nyquist input frequency for the worst case. The DNL/INL is improved from 5.02/5.6 LSB to 0.25/0.38 LSB, respectively. ©2009 IEEE.