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A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer Journal article
Cao, Yuefeng, Zhang, Minglei, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024.
Authors:  Cao, Yuefeng;  Zhang, Minglei;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2024/07/04
Analog-to-digital Converter (Adc)  Process, Supply Voltage, And Temperature (Pvt)-robust  Sturdy Ring Amplifier (sRingamp)  Time-domain Quantizer  Time-to-digital Converter (Tdc)  Voltage-to-time Converter (Vtc)  
A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS Journal article
Lu, Xin, Wu, Jiangchao, Wang, Zhao, Xiang, Yifei, Liu, Liyuan, Mak, Pui In, Martins, Rui P., Law, Man Kay. A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(8), 3635 - 3639.
Authors:  Lu, Xin;  Wu, Jiangchao;  Wang, Zhao;  Xiang, Yifei;  Liu, Liyuan; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2024/05/16
Coarse-fine Conversion  Cyclic Time-to-digital Converter (Tdc)  Delays  Gated-ring Oscillator (Gro)  Generators  Image Edge Detection  Logic Gates  Phase Domain Reset  Ring Oscillators  Signal Resolution  Switches  
Low-Power Nyquist ADCs Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:131-180
Authors:  Minglei Zhang;  Chi-Hang Chan;  Yan Zhu;  Rui P. Martins
Favorite | TC[Scopus]:1 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Calibration  Low Supply Voltage  Pipeline  Successive Approximation Register (Sar)  Time-domain Converter (Tdc)  
A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components Journal article
Zhang, Mengdi, Zhao, Ye, Chen, Yong, Crovetti, Paolo, Wang, Yanji, Ning, Xinshun, Qiao, Shushan. A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components[J]. Sensors (Basel, Switzerland), 2022, 22(22), 8936.
Authors:  Zhang, Mengdi;  Zhao, Ye;  Chen, Yong;  Crovetti, Paolo;  Wang, Yanji; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:3.4/3.7 | Submit date：2022/09/07
Analog-to-digital Converter (Adc)  Differential Nonlinearity (Dnl)  Effective Number Of Bits (Enob)  Fpga  Integral Nonlinearity (Inl)  Time-to-digital Converter (Tdc)  
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
Chen, Peng, Yin, Jun, Zhang, Feifei, Mak, Pui In, Martins, Rui P., Staszewski, Robert Bogdan. Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), 196-206.
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.; et al.
Favorite | TC[WOS]:5 TC[Scopus]:7  IF:5.2/4.5 | Submit date：2021/09/20
All-digital Pll (adPll)  Build-in Self-test (Bist)  Digital-to-time Converter (Dtc)  Fractional Spur  Jitter  Mismatch  Noise Shaping  Phase/frequency Detector (Pfd)  Phase Frequency Detectors  Self Calibration  Time-to-digital Converter (Tdc).  
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps Journal article
Zhang,Minglei, Zhu,Yan, Chan,Chi Hang, Martins,Rui P.. An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps[J]. IEEE Journal of Solid-State Circuits, 2020, 55(12), 3225-3235.
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite | TC[WOS]:34 TC[Scopus]:38  IF:4.6/5.6 | Submit date：2021/03/04
Analog-to-digital Converter (Adc)  High-speed Adc  Metastability  Process  Supply Voltage  And Temperature (Pvt) Robustness  Time Interpolation  Time Residue  Time-domain Adc  Time-to-digital Converter (Tdc)  
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques Journal article
Zhang,Minglei, Chan,Chi Hang, Zhu,Yan, Martins,Rui P.. A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques[J]. IEEE Journal of Solid-State Circuits, 2019, 54(12), 3396-3409.
Authors:  Zhang,Minglei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:27 TC[Scopus]:40  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Low Power Supply  Process  Voltage  And Temperature (Pvt) Robustness  Successive Approximation Register (Sar)  Threshold Crossing Detector  Time Residue Generator (Trg)  Time-domain Adc  Time-to-digital Converter (Tdc)  Two-step Tdc  Voltage-to-time Converter (Vtc)