Analog-to-digital converters (ADCs) bridge the analog and digital worlds, which often confines the system’s performance. In portable or Internet of Things devices, the power budget is extremely tight, calling for low-power ADCs and sometimes even low supply voltage. While with a more complex modulation scheme and crowded spectrum utilization, a large dynamic range is still essential, motivating innovation in circuit, calibration, and architecture levels in the ADC designs. This chapter discusses four Nyquist ADC designs with outstanding energy efficiency. The first is a single-channel 12b 1GS/s ADC with a three-stage pipeline SAR architecture. We introduce next a SAR-TDC hybrid architecture, realizing 20 MS/s with 13b resolution. The third work is a pure pipeline ADC with a new timing arrangement, enabling a single-channel 3.3 GS/s 6b design. The last design is a time-interleaved 8b 10 GS/s TDC-based ADC. This chapter sets forth all the detailed design considerations of the four circuits.