Ring amplifier (RingAmp)-based multiplying digital-to-analog converters (MDACs) feature high energy efficiency and linearity; however, their process, supply voltage, and temperature (PVT)-sensitive transient responses require significant timing overhead, limiting the speed of the pipelined analog-to-digital converters (ADCs). This work introduces a sturdy RingAmp (SRingAmp), which stabilizes the gain, gain–bandwidth product (GBW), phase margin (PM), and transient response by building up compensatory coordination, achieving significant speed and PVT-robustness advantages over prior RingAmps. Furthermore, a time-domain ADC is utilized as the sub-quantizer with two techniques, including a common-mode shifting (CMS) scheme and a partial power-down (PD) operation for the voltage-to-time converter (VTC) and the time-to-digital converter (TDC), respectively. The former allows a near mid-supply common-mode input without degrading the linearity, and the latter improves the power efficiency. With these techniques, a single-channel 12-bit pipelined ADC achieves 2 GS/s in 28-nm CMOS with measured 60.4-dB SNDR and 75.8-dB SFDR at a Nyquist input, consuming 27 mW from a 1.0-V supply and yielding a Schreier figure of merit (FoM) of 166.1 dB.