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A 0.6 V 8b 100MS/s SAR ADC with Minimized DAC capacitance and switching energy in 65nm CMOS Conference paper
Wu, W. N., Zhu, Y., Ding, L., Chan, C. H., Chio, U. F., Sin, S. W., U, S. P., Martins, R. P.. A 0.6 V 8b 100MS/s SAR ADC with Minimized DAC capacitance and switching energy in 65nm CMOS[C], 2013.
Authors:  Wu, W. N.;  Zhu, Y.;  Ding, L.;  Chan, C. H.;  Chio, U. F.; et al.
Favorite |  | Submit date：2022/01/25
Switching Scheme  SAR ADC  DAC Design  
Circuit Techniques for High-Performance SAR-Type ADCs Thesis
Zhu, Y., Sin, S. W., U, S.P., Martins, R. P.. Circuit Techniques for High-Performance SAR-Type ADCs[D], 2011.
Authors:  Zhu, Y.;  Sin, S. W.;  U, S.P.;  Martins, R. P.
Favorite |  | Submit date：2022/01/24
SAR ADC  Ppelined SAR ADC  Low Power Technique  Switching Scheme