| Status | 已發表Published |
| A 0.6 V 8b 100MS/s SAR ADC with Minimized DAC capacitance and switching energy in 65nm CMOS | |
Wu, W. N. ; Zhu, Y.; Ding, L.; Chan, C. H.; Chio, U. F.; Sin, S. W.; U, S. P.; Martins, R. P.
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| 2013-05-19 | |
| Source Publication | 2013 IEEE International Symposium on Circuits and Systems
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| Abstract | This paper presents a monotonic multi-switching technique that is implemented in a 8b SAR ADC. The proposed switching reduces 1/2 total DAC capacitance and achieves more than 80% switching energy saving when compared to the most advanced VCM-based or merged capacitor switching methods. Besides, conversion redundancies are added to compensate the errors resulting from insufficient DAC settling and reference noise. The proposed 8-bit SAR ADC operates at 100MS/s with 0.6V supply in 65nm CMOS. The simulation results show that the design achieves 48.8dB SNDR with only 0.524mW power. The Figure-of-Merit (FoM) is 23.35fJ/conversion-step. |
| Keyword | Switching Scheme SAR ADC DAC Design |
| Language | 英語English |
| The Source to Article | PB_Publication |
| PUB ID | 38540 |
| Document Type | Conference paper |
| Collection | DEPARTMENT OF GLOBAL LEGAL STUDIES |
| Recommended Citation GB/T 7714 | Wu, W. N.,Zhu, Y.,Ding, L.,et al. A 0.6 V 8b 100MS/s SAR ADC with Minimized DAC capacitance and switching energy in 65nm CMOS[C], 2013. |
| APA | Wu, W. N.., Zhu, Y.., Ding, L.., Chan, C. H.., Chio, U. F.., Sin, S. W.., U, S. P.., & Martins, R. P. (2013). A 0.6 V 8b 100MS/s SAR ADC with Minimized DAC capacitance and switching energy in 65nm CMOS. 2013 IEEE International Symposium on Circuits and Systems. |
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