| Status | 已發表Published |
| Title | Circuit Techniques for High-Performance SAR-Type ADCs |
| Author | Zhu, Y.; Sin, S. W.; U, S.P.; Martins, R. P. |
| Date Issued | 2011-11-30 |
| Keyword | SAR ADC Ppelined SAR ADC Low Power Technique Switching Scheme |
| Abstract | ADCs play an important role in modern electronic, like wireless networks and digital TV applications, where an ADC with a medium conversion rate and a medium resolution is necessary. Pipelined ADCs are widely used in these applications. However, great reductions in power consumption and chip area are required by portable devices. Then, pipelined ADCs with requirement of power hungry operational amplifiers are not suitable for low power applications. With the feature size of CMOS devices scaling down, more digitized ADC architectures like Successive Approximation Register (SAR) ADC have re-emerged as an alternative to pipelined ADC. Nevertheless, the reference buffer, capacitor mismatch and feedback control loop are usually the bottleneck of the SAR ADC to target for high-speed and high-resolution applications. This thesis will propose multiple circuit techniques to improve the power efficiency and speed of SAR and Time-Interleaved (TI) pipelined-SAR ADCs. The first part focuses on the analysis of the single channel SAR ADC. Initially, the power and speed limitations of the conventional SAR ADC are addressed, and two power saving techniques, namely VDD-referenced and Vcm-based switching will be proposed. Subsequently, the mathematical analysis of the conversion power and linearity are derived and verified through behavioral simulations. In addition, a code-randomized digital calibration method is also proposed to improve the linearity of conventional switching. Finally, two 1.2V 10-bit VDD referenced SAR ADCs with conventional switching and Vcm-based switchinng fabricated in 90nm CMOS are analyzed to verify the proposed circuit techniques and corresponding power and linearity analysis. The second part of this thesis concentrates on the analysis of the TIpipelined-SAR ADC. The impact of the implementation with the time interleaved scheme that degrades the conversion performance, including offset, gain and timing mismatches are firstly analyzed and discussed. The capacitive attenuation solutions in both 1st and 2nd DACs and wide-range offset calibration technique are then proposed to optimize the power dissipation, conversion accuracy and speed. Finally, a 1.1-V, 10-b 160MS/s TI pipelined-SAR ADC which encompasses all the circuit techniques mentioned above in 65nm CMOS will be demonstrated with through measurement results. The achieved high Figure-of-Merit (FoM) of this prototype validates the effectiveness of the proposed high power-efficiency and high-speed techniques in the thesis. |
| Language | 英語English |
| PUB ID | 38598 |
| Document Type | Thesis |
| Collection | DEPARTMENT OF PSYCHOLOGY |
| Recommended Citation GB/T 7714 | Zhu, Y.,Sin, S. W.,U, S.P.,et al. Circuit Techniques for High-Performance SAR-Type ADCs[D], 2011. |
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