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Sub-threshold VLSI-Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques Conference paper
Li, M., Ieong, C. I., Law, M. K., Mak, P. I., Vai, M. I., Pun, S. H., Martins, R. P.. Sub-threshold VLSI-Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques[C], 2016.
Authors:  Li, M.;  Ieong, C. I.;  Law, M. K.;  Mak, P. I.;  Vai, M. I.; et al.
Favorite |  | Submit date：2022/01/24
Sub-threshold Logic  Unbalanced Pull-up/down Network  Logical Effort  Inverse-Narrow-Width Effect  
Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques Journal article
Li, M., Ieong, C. I., Law, M. K., Mak, P. I., Vai, M. I., Pun, S. H., Martins, R. P.. Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques[J]. IEEE Transactions on Very large scale integration systems, 2015, 3119-3123.
Authors:  Li, M.;  Ieong, C. I.;  Law, M. K.;  Mak, P. I.;  Vai, M. I.; et al.
Favorite |   IF:2.8/2.8 | Submit date：2022/01/24
CMOS  Electrocardiography (ECG)  device sizing  finite impulse response (FIR) filter  inverse-narrow-width (INW)  logical effort  process-voltage-temperature (PVT) variations  sub-threshold standard logic library  ultra-low-energy  ultra-low-voltage