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A low dropout regulator with PSR under-48dB up to 20GHz for a SARADC reference buffer Conference paper
Yi Zeng, Chi-Hang Chan, Yan Zhu, Rui P. Martins. A low dropout regulator with PSR under-48dB up to 20GHz for a SARADC reference buffer[C], 2022.
Authors:  Yi Zeng;  Chi-Hang Chan;  Yan Zhu;  Rui P. Martins
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2023/03/06
Low Dropout Regulator (Ldo)  High Power Supply Rejection (Psr)  Reference Buffer  Successive-approximation-register (Sar)  Analog-to-digital Converter (Adc)  
An Auxiliary-Loop-Enhanced Fast-Transient FVF LDO as Reference Buffer of a SAR ADC Conference paper
Zeng, Yi, Chan, Chi Hang, Zhu, Yan, Martins, Rui P.. An Auxiliary-Loop-Enhanced Fast-Transient FVF LDO as Reference Buffer of a SAR ADC[C], 2022, 2660-2664.
Authors:  Zeng, Yi;  Chan, Chi Hang;  Zhu, Yan;  Martins, Rui P.
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2023/01/30
Analog-to-digital Converter (Adc)  Flipped Voltage Follower (Fvf)  Reference Buffer  Successive Approximation Register (Sar)  
Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC Journal article
Li, Cheng, Chan, Chi-Hang, Zhu, Yan, Martins, Rui P.. Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66(1), 82-93.
Authors:  Li, Cheng;  Chan, Chi-Hang;  Zhu, Yan;  Martins, Rui P.
Favorite | TC[WOS]:11 TC[Scopus]:14  IF:5.2/4.5 | Submit date：2019/01/17
Reference Error  Reference Buffer  Successive-approximation-register (Sar)  Analog-to-digital Converter (Adc)  Reference Ripple  
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration Journal article
Chan, Chi-Hang, Zhu, Yan, Li, Cheng, Zhang, Wai-Hong, Ho, Iok-Meng, Wei, Lai, Seng-Pan, U., Martins, Rui Paulo. 60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52(10), 2576-2588.
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Li, Cheng;  Zhang, Wai-Hong;  Ho, Iok-Meng; et al.
Favorite | TC[WOS]:38 TC[Scopus]:46  IF:4.6/5.6 | Submit date：2018/10/30
Reference Buffer  Reference Error Calibration  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Threshold Reconfigurable Comparator  
On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC Conference paper
Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R. P. Martins. On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC[C], 2005, 276-280.
Authors:  Weng-Ieng Mok;  Pui-In Mak;  Seng-Pan U;  R. P. Martins
Favorite |  | Submit date：2019/02/28
High-speed  Pipelined Analog-to-digital Converter  Reference Voltage  Voltage Buffer