The operating principle of pipelined analog-to-digital converter (ADC) is to subtract, sequentially along the cascaded stages, different reference voltages from the analog sample. This operation, nevertheless, creates internally an input-dependent fluctuation on the reference voltage. Such kind of signal-dependent error cannot be eliminated by trimming and/or calibration. The effect is especially significant at very-high conversion rate, since conventional method for stabilizing the reference voltage with large off-chip capacitor is no longer appropriate, as such a capacitor will resonate with the package inductance. However, on-chip generates a stable and high-speed reference not only consumes large power and area, but also makes the reference voltage highly sensitive to internal noises. This paper, first, presents an in-depth investigation on the causes and effects of unsteady reference voltage. Then, an effective model scheme is carried out and verified by circuit simulations. Finally, two on-chip reference voltage compensation techniques, which can effectively eliminate the error without the aforementioned drawbacks and feature compact in size, are proposed