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A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator Journal article
Zhang, Hongshuai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3565-3575.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:4.6/5.6 | Submit date：2024/01/02
Analog-to-digital Converter (Adc)  Auxiliary Noise Shaping (Ns) Successive-approximation Register (Sar) Adc  Capacitor Stacking  Data-weighted Averaging And detect-And-skip (Dwa And Das)  Differential Sampling  Energy Efficient  Error SupprEssion (Es) And Reconstruction  Gain Error Shaping (Ges)  Partial Time Interleaving  Passive Ns  Pipelined Sar  Quantization Predication Unrolled  Two-step Floating Inverter Amplifier (Fia)  
A 10MHz-BW 85dB-DR CT 0-4 MASH Delta-Sigma Modulator Achieving +5dBFS MSA Journal article
Tan Gaofeng, Qin Xinyu, Liu Yan, Guo Mingqiang, Sin Sai-Weng, Wang Guoxing, Lian Yong, Qi Liang. A 10MHz-BW 85dB-DR CT 0-4 MASH Delta-Sigma Modulator Achieving +5dBFS MSA[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023.
Authors:  Tan Gaofeng;  Qin Xinyu;  Liu Yan;  Guo Mingqiang;  Sin Sai-Weng; et al.
Adobe PDF | Favorite |   IF:5.2/4.5 | Submit date：2023/08/22
Multi-stage Noise Shaping , Topology , Delays , Robustness , Quantization (Signal) , Calibration , Thermal Stability  
Wideband Continuous-time MASH Delta-Sigma Modulators: A Tutorial Review Journal article
Qi, Liang, Liu, Yuekai, Sin, Sai Weng, Xing, Xinpeng, Wang, Guoxing, Ortmanns, Maurits, Martins, Rui P.. Wideband Continuous-time MASH Delta-Sigma Modulators: A Tutorial Review[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(6), 2623-2628.
Authors:  Qi, Liang;  Liu, Yuekai;  Sin, Sai Weng;  Xing, Xinpeng;  Wang, Guoxing; et al.
Favorite | TC[WOS]:12 TC[Scopus]:12  IF:4.0/3.7 | Submit date：2022/05/17
Delta-sigma Modulator (Dsm)  Continuoustime (Ct)  Multi-stage Noise-shaping (Mash)  Sturdy Mash  Quantization Noise (Qn)  Qn Leakage  Qn Extraction  
An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration Journal article
Zhang, Hongshuai, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57(5), 1480-1491.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite | TC[WOS]:8 TC[Scopus]:10  IF:4.6/5.6 | Submit date：2022/05/13
Amplifier Linearity Enhancement  Analog-to-digital Converter (Adc)  Background Offset Calibration  Digital Reconstruction Filter  Dwa  Energy And Area Efficient  Inherent Gain Error Tolerant  Inter-stage Gain Error  Noise Shaping (Ns)  Oversampling  Partial Interleaving  Pipelined Successive Approximation (Sar)  Quantization Leakage Error  
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration Journal article
Zhang, Qihui, Ning, Ning, Zhang, Zhong, Li, Jing, Wu, Kejun, Chen, Yong, Yu, Qi. A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration[J]. IEEE Journal of Solid-State Circuits, 2022, 57(7), 2181-2195.
Authors:  Zhang, Qihui;  Ning, Ning;  Zhang, Zhong;  Li, Jing;  Wu, Kejun; et al.
Favorite | TC[WOS]:22 TC[Scopus]:24  IF:4.6/5.6 | Submit date：2022/05/17
Analog-to-digital Converter (Adc)  Calibration  Capacitors  Delays  Dither-based Digital Calibration  Finite Impulse Response Filters  Hybrid Error Control Structure  Noise Shaping  Noise Shaping (Ns)  Quantization (Signal)  Successive Approximation Register (Sar).  Topology  
A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp Journal article
Xing, K., Wang, W., Zhu, Y., Chan, C. H., Martins, R. P.. A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 64-74.
Authors:  Xing, K.;  Wang, W.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2023/08/31
Analog-to-digital conversion (ADC)  continuous-time delta-sigma modulator (CTDSM)  SAB-ELD- merged integrator  three-stage Opamp  preliminary sampling and quantization (PSQ) technique  high-speed noise-shaping SAR (NS-SAR)  
A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp Journal article
Xing, Kai, Wang, Wei, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), 64-74.
Authors:  Xing, Kai;  Wang, Wei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite | TC[WOS]:5 TC[Scopus]:5  IF:5.2/4.5 | Submit date：2021/09/20
Analog-to-digital Conversion (Adc)  Continuous-time Delta-sigma Modulator (Ctdsm)  Gain  High-speed Noise-shaping Sar (ns-Sar).  Loading  Low-frequency Noise  Modulation  Preliminary Sampling And Quantization (Psq) Technique  Quantization (Signal)  Sab-eld-merged Integrator  Three-stage Opamp  Topology  Wideband  
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection Journal article
Un,Ka Fai, Zhang,Feifei, Mak,Pui In, Martins,Rui P., Zhu,Anding, Staszewski,Robert Bogdan. Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, 67(1), 37-41.
Authors:  Un,Ka Fai;  Zhang,Feifei;  Mak,Pui In;  Martins,Rui P.;  Zhu,Anding; et al.
Favorite | TC[WOS]:5 TC[Scopus]:5  IF:4.0/3.7 | Submit date：2021/03/09
Digital Baseband  Digital Transmitter (Dtx)  Linear Interpolation  Modulation  Noise Filtering  Out-of-band Noise  Quantization Noise  Replicas  
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
Qi,Liang, Jain,Ankesh, Jiang,Dongyang, Sin,Sai Weng, Martins,Rui P., Ortmanns,Maurits. A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 344-355.
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.; et al.
Favorite | TC[WOS]:54 TC[Scopus]:48  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)  
A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
Qi, L., Jain, A., Jiang, D., Sin, S. W., Martins, R. P., Ortmanns, M.. A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 344-355.
Authors:  Qi, L.;  Jain, A.;  Jiang, D.;  Sin, S. W.;  Martins, R. P.; et al.
Favorite | TC[WOS]:54 TC[Scopus]:48  IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)