This article presents a second-order noise shaping (NS) pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with fully passive NS and a second-order gain error shaping (GES) based on a Quantization-Prediction-Unrolled scheme. The GES is enabled by subtracting the residue voltage with a predicted quantization error through a second-order digital GES filter. Utilizing an auxiliary SAR ADC for the prediction retains an outstanding GES ability and avoids deteriorating the residue amplifier's (RAs) linearity as in the conventional GES scheme. The NS also applies to the auxiliary SAR ADC to further ease the overhead from the GES techniques. Besides, a second-order fully passive NS SAR ADC is presented in the backend stage of the overall pipelined SAR architecture, which only calls for a single additional small-size input pair in the comparator, mitigating the noise penalty from the high-order passive NS scheme. Furthermore, a two-step floating inverter amplifier (FIA) is introduced, alleviating the severe gain variation over process-voltage-temperature (PVT) in the conventional one-step counterpart and eventually allowing the energy-efficient open-loop FIA to fit our architecture. With partial time interleaving, the ADC in a 28-nm CMOS process runs at 400 MS/s, achieving 25 MHz bandwidth and 77.2 dB nominal signal-to-noise-and-distortion-ratio (SNDR) with 8 × OSR. It consumes 2.03 mW power from a 1-V supply and exhibits a 178-dB Schreier figure-of-merit (FoMS). The SNDR of the ADC deviates less than 3-dB from the nominal performance within-24% to +18% gain error.