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A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance | |
Qi, L.1,2; Jain, A.3; Jiang, D.1,2; Sin, S. W.1,2; Martins, R. P.4,5; Ortmanns, M.6 | |
2019-10-08 | |
Source Publication | IEEE Journal of Solid-State Circuits |
ISSN | 0018-9200 |
Volume | 55Issue:2Pages:344-355 |
Abstract | This article presents a dual-loop noise-coupling (NC)-assisted continuous-time (CT) sturdy multistage noise-shaping (SMASH) ΔΣ modulator (DSM), employing 1.5-bit/4-bit quantizers. The proposed SMASH can equivalently work as an overall fourth-order DSM with 4-bit internal quantization. The NC applied in this CT SMASH DSM whitens the 1.5-bit quantization noise (QN) and further reduces its in-band tone power, while a finite-impulse response (FIR) filter integrated into the outermost feedback path suppresses the out-of-band (OOB) noise power of the multibit digital-to-analog converter (DAC) input. Together, they avoid any linearization technique for the multibit DAC. Sampled at 1.2 GHz, the 28-nm CMOS experimental prototype measures a signal-to-noise-and-distortion ratio (SNDR) of 76.6 dB and a spurious-free dynamic range (SFDR) of 87.9 dB over a 50-MHz bandwidth (BW), consuming 29.2 mW from 1.2-V/1.5-V supplies and occupying an active area of 0.085 mm 2 . It exhibits a Schreier figure-of-merit (FoM) (SNDR) of 168.9 dB. |
Keyword | Analog-to-digital Converter (Adc) Continuous Time (Ct) Digital-to-analog Converter (Dac) Linearization Excess Loop Delay (Eld) Compensation Filter Finite-impulse Response (Fir) Multibit Quantization Noise Coupling (Nc) Sturdy Multistage Noise-shaping (Smash) Successive-approximation Register (Sar) |
DOI | 10.1109/JSSC.2019.2942359 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000510725300011 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
The Source to Article | PB_Publication |
Scopus ID | 2-s2.0-85079674831 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | INSTITUTE OF MICROELECTRONICS Faculty of Science and Technology DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Corresponding Author | Sin, S. W. |
Affiliation | 1.State-Key Laboratory of Analog and Mixed-Signal VLSI,Institute of Microelectronics,University of Macau,999078,Macao 2.Department of Electrical and Computer Engineering,Faculty of Science and Technology,University of Macau,999078,Macao 3.Electrical Engineering Department,IIT Delhi,New Delhi,110016,India 4.Department of Electrical and Computer Engineering,University of Macau,State-Key Laboratory of Analog and Mixed-Signal VLSI,Institute of Microelectronics,Faculty of Science and Technology,999078,Macao 5.Instituto Superior Técnico,Universidade de Lisboa,Lisbon,1649-004,Portugal 6.Faculty of Engineering,Computer Science and Psychology,Institute of Microelectronics,University of Ulm,Ulm,89081,Germany |
First Author Affilication | University of Macau; Faculty of Science and Technology |
Corresponding Author Affilication | University of Macau; Faculty of Science and Technology |
Recommended Citation GB/T 7714 | Qi, L.,Jain, A.,Jiang, D.,et al. A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 344-355. |
APA | Qi, L.., Jain, A.., Jiang, D.., Sin, S. W.., Martins, R. P.., & Ortmanns, M. (2019). A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance. IEEE Journal of Solid-State Circuits, 55(2), 344-355. |
MLA | Qi, L.,et al."A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance".IEEE Journal of Solid-State Circuits 55.2(2019):344-355. |
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