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An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R Journal article
Xu, Zixuan, Xing, Kai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R[J]. IEEE Journal of Solid-State Circuits, 2024, 59(3), 753-764.
Authors:  Xu, Zixuan;  Xing, Kai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/04/02
Ac-coupled Negative-r  Analog-to-digital Conversion (Adc)  Continuous-time Sigma-delta Modulator (Ct Sdm)  Noise-shaping Continuous Time Successive-approximation Register (Ns Ct-sar)  
A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator Journal article
Zhang, Hongshuai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3565-3575.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:4.6/5.6 | Submit date：2024/01/02
Analog-to-digital Converter (Adc)  Auxiliary Noise Shaping (Ns) Successive-approximation Register (Sar) Adc  Capacitor Stacking  Data-weighted Averaging And detect-And-skip (Dwa And Das)  Differential Sampling  Energy Efficient  Error SupprEssion (Es) And Reconstruction  Gain Error Shaping (Ges)  Partial Time Interleaving  Passive Ns  Pipelined Sar  Quantization Predication Unrolled  Two-step Floating Inverter Amplifier (Fia)  
High-Performance Oversampling ADCs Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:181-218
Authors:  Chi-Hang Chan;  Yan Zhu;  Liang Qi;  Sai Weng Sin;  Maurits Ortmanns; et al.
Favorite | TC[Scopus]:0 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Cmos  Continuous-time Dsm (Ct Dsm)  Delta-sigma Modulator (Dsm)  Noise Shaping (Ns)  Oversampling  Pipeline Sar Adc  Successive Approximation Register (Sar)  
A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward Journal article
Zhao,Shulin, Guo,Mingqiang, Qi,Liang, Xu,Dengke, Wang,Guoxing, Martins,Rui P., Sin,Sai Weng. A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward[J]. IEEE Journal of Solid-State Circuits, 2023, 58(10), 2722-2732.
Authors:  Zhao,Shulin;  Guo,Mingqiang;  Qi,Liang;  Xu,Dengke;  Wang,Guoxing; et al.
Adobe PDF | Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2023/08/03
Error-feedforward (Ff)  Midway Error-feedback (Fb)  Noise Transfer Function (Ntf) Peaking  Offset Reduction  Redundancy  Time-interleaving Noise-shaping Successive Approximation Register (Ns-sar)  
An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration Journal article
Zhang, Hongshuai, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57(5), 1480-1491.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite | TC[WOS]:8 TC[Scopus]:10  IF:4.6/5.6 | Submit date：2022/05/13
Amplifier Linearity Enhancement  Analog-to-digital Converter (Adc)  Background Offset Calibration  Digital Reconstruction Filter  Dwa  Energy And Area Efficient  Inherent Gain Error Tolerant  Inter-stage Gain Error  Noise Shaping (Ns)  Oversampling  Partial Interleaving  Pipelined Successive Approximation (Sar)  Quantization Leakage Error  
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations Journal article
Zhang, Yanbo, Zhang, Jin, Liu, Shubin, Ding, Ruixue, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations[J]. IEEE Journal of Solid-State Circuits, 2022, 57(3), 745-756.
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Ding, Ruixue;  Zhu, Yan; et al.
Favorite | TC[WOS]:7 TC[Scopus]:10  IF:4.6/5.6 | Submit date：2022/03/28
Analog-to-digital Converter (Adc)  Inter-stage Gain And Offset Calibrations  Noise-shaping (Ns)  Split Adc  Successive Approximation Register (Sar)-assisted Pipeline  
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration Journal article
Zhang, Qihui, Ning, Ning, Zhang, Zhong, Li, Jing, Wu, Kejun, Chen, Yong, Yu, Qi. A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration[J]. IEEE Journal of Solid-State Circuits, 2022, 57(7), 2181-2195.
Authors:  Zhang, Qihui;  Ning, Ning;  Zhang, Zhong;  Li, Jing;  Wu, Kejun; et al.
Favorite | TC[WOS]:22 TC[Scopus]:24  IF:4.6/5.6 | Submit date：2022/05/17
Analog-to-digital Converter (Adc)  Calibration  Capacitors  Delays  Dither-based Digital Calibration  Finite Impulse Response Filters  Hybrid Error Control Structure  Noise Shaping  Noise Shaping (Ns)  Quantization (Signal)  Successive Approximation Register (Sar).  Topology  
A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp Journal article
Xing, K., Wang, W., Zhu, Y., Chan, C. H., Martins, R. P.. A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 64-74.
Authors:  Xing, K.;  Wang, W.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2023/08/31
Analog-to-digital conversion (ADC)  continuous-time delta-sigma modulator (CTDSM)  SAB-ELD- merged integrator  three-stage Opamp  preliminary sampling and quantization (PSQ) technique  high-speed noise-shaping SAR (NS-SAR)  
A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC Conference paper
Li, Ke, Sin, Sai Weng, Qi, Liang, Zhao, Weibing, Wang, Guoxing, Martins, R. P.. A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC[C], 2022, 551-555.
Authors:  Li, Ke;  Sin, Sai Weng;  Qi, Liang;  Zhao, Weibing;  Wang, Guoxing; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3 | Submit date：2023/01/30
Delta-sigma Modulator (Dsm)  Hybrid Adc  Multi-stage Noise-shaping (Mash)  Noise-shaping Successive Approximation Register (Ns-sar)  
A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp Journal article
Xing, Kai, Wang, Wei, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), 64-74.
Authors:  Xing, Kai;  Wang, Wei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite | TC[WOS]:5 TC[Scopus]:5  IF:5.2/4.5 | Submit date：2021/09/20
Analog-to-digital Conversion (Adc)  Continuous-time Delta-sigma Modulator (Ctdsm)  Gain  High-speed Noise-shaping Sar (ns-Sar).  Loading  Low-frequency Noise  Modulation  Preliminary Sampling And Quantization (Psq) Technique  Quantization (Signal)  Sab-eld-merged Integrator  Three-stage Opamp  Topology  Wideband