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Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review Journal article
Guo, Mingqiang, Sin, Sai Weng, Qi, Liang, Xu, Dengke, Wang, Guoxing, Martins, Rui P.. Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(6), 2564 - 2569.
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke;  Wang, Guoxing; et al.
Adobe PDF | Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2022/05/17
Adc  Time-interleaved  Timing Mismatch  Background  Calibration.  
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
Chen, Peng, Yin, Jun, Zhang, Feifei, Mak, Pui In, Martins, Rui P., Staszewski, Robert Bogdan. Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), 196-206.
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.; et al.
Favorite | TC[WOS]:5 TC[Scopus]:7  IF:5.2/4.5 | Submit date：2021/09/20
All-digital Pll (adPll)  Build-in Self-test (Bist)  Digital-to-time Converter (Dtc)  Fractional Spur  Jitter  Mismatch  Noise Shaping  Phase/frequency Detector (Pfd)  Phase Frequency Detectors  Self Calibration  Time-to-digital Converter (Tdc).  
Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs Conference paper
Guo Mingqiang, Sin Sai-Weng, Rui P. Martins. Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs[C]:IEEE, 2021, 248 - 249.
Authors:  Guo Mingqiang;  Sin Sai-Weng;  Rui P. Martins
Adobe PDF | Favorite | TC[WOS]:0 TC[Scopus]:2 | Submit date：2022/05/13
Adc  Background Calbration  Mismatch Calibration  Time-interleaved Converter  Timing Mismatch  
A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications Journal article
Guo,Mingqiang, Mao,Jiaji, Sin,Sai Weng, Wei,Hegong, Martins,Rui P.. A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications[J]. IEEE Access, 2020, 8, 138944-138954.
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Adobe PDF | Favorite | TC[WOS]:17 TC[Scopus]:22  IF:3.4/3.7 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Digital Background Calibration  Digital-mixing  Time-interleaved (Ti) Adc  Timing Mismatch  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
Guo,Mingqiang, Mao,Jiaji, Sin,Sai Weng, Wei,Hegong, Martins,Rui P.. A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration[J]. IEEE Journal of Solid-State Circuits, 2020, 55(3), 693-705.
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Adobe PDF | Favorite | TC[WOS]:50 TC[Scopus]:53  IF:4.6/5.6 | Submit date：2021/03/04
Analog-to-digital Converter (Adc)  Digital Background Calibration  Split Adc  Time-interleaved (Ti) Adc  Timing-skew Mismatch  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration Journal article
Guo Mingqiang, Mao Jiaji, Sin Sai-Weng, Wei Hegong, Rui P. Martins. A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration[J]. IEEE Journal of Solid-State Circuits, 2020, 55(3), 693-705.
Authors:  Guo Mingqiang;  Mao Jiaji;  Sin Sai-Weng;  Wei Hegong;  Rui P. Martins
Adobe PDF | Favorite | TC[WOS]:50 TC[Scopus]:53  IF:4.6/5.6 | Submit date：2022/08/20
Analog-to-Digital Converter (Adc), Digital Background CalibraTion, Split Adc, Time-interleaved (Ti) Adc, Timing-skew Mismatch  
A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration Conference paper
Guo, M., Mao, J., Sin, S. W., Wei, H., Martins, R. P.. A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration[C], 2019.
Authors:  Guo, M.;  Mao, J.;  Sin, S. W.;  Wei, H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
SAR analog-to-digital converter (ADC)  time-interleaved (TI) ADC  timing-skew calibration  split ADC  background mismatch calibration  
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration Conference paper
Guo,Mingqiang, Mao,Jiaji, Sin,Sai Weng, Wei,Hegong, Martins,R. P.. A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2019, 8780222.
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,R. P.
Adobe PDF | Favorite | TC[WOS]:13 TC[Scopus]:9 | Submit date：2021/03/09
Sar Analog-to-digital Converter (Adc)  Time-interleaved (Ti) Adc  Timing-skew Calibration  Split Adc  Background Mismatch Calibration  
Digital Assisted Techniques for Bridge DAC Capacitor Mismatch Calibration in SAR ADC Thesis
Wang , G.C., Zhu, Y., Chan, C. H., U, S.P.. Digital Assisted Techniques for Bridge DAC Capacitor Mismatch Calibration in SAR ADC[D], 2017.
Authors:  Wang , G.C.;  Zhu, Y.;  Chan, C. H.;  U, S.P.
Favorite |  | Submit date：2023/08/31
Bridge DAC  Capacitor Mismatch Calibration  SAR ADC  
An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs Conference paper
Li D., Sin S.-W., Seng-Pan U., Martins R.P.. An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs[C], 2010, 208-211.
Authors:  Li D.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | TC[WOS]:2 TC[Scopus]:3 | Submit date：2019/02/11
Capacitor Mismatch  Digital Calibration  Interstage Gain Error  Pipelined Adcs