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A 167-μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double-Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO Journal article
Shao, Haijun, Martins, Rui P., Mak, Pui In. A 167-μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double-Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Shao, Haijun;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/11/05
Adjacent Channel  Bluetooth Low Energy (Ble)  Cascaded  Cmos  Double Balanced  Figure Of Merit (Fom)  Hybrid Coupler  Noise Figure (Nf)  Notching  Out Of Band (Oob)  Passive Intensive  Phase Noise (Pn)  Quadrature  Signal-to-noise Ratio (Snr)  Spurious-free Dynamic Range (Sfdr)  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)  
A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Phase Locked Loops  Type-i  
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
Chen, Peng, Meng, Xi, Yin, Jun, Mak, Pui In, Martins, Rui P., Staszewski, Robert Bogdan. A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(1), 51-63.
Authors:  Chen, Peng;  Meng, Xi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.; et al.
Favorite | TC[WOS]:16 TC[Scopus]:15  IF:5.2/4.5 | Submit date：2021/09/20
Adpll  Bluetooth Le (bLe)  Dco  Fractionaln Pll  Phase Noise (Pn)  Tdc  Dtc  Inverse-class-f  Low Power  The Iot  
An Ultralow Phase Noise Eight-Core Fundamental 62-To-67-GHz VCO in 65-nm CMOS Journal article
Zhang, Jingzhi, Zhao, Chenxi, Wu, Yunqiu, Liu, Huihua, Zhu, Yan, Kang, Kai. An Ultralow Phase Noise Eight-Core Fundamental 62-To-67-GHz VCO in 65-nm CMOS[J]. IEEE Microwave and Wireless Components Letters, 2019, 29(2), 125-127.
Authors:  Zhang, Jingzhi;  Zhao, Chenxi;  Wu, Yunqiu;  Liu, Huihua;  Zhu, Yan; et al.
Favorite | TC[WOS]:15 TC[Scopus]:17  IF:2.9/3.0 | Submit date：2022/04/15
Coupled-vco  Fundamental  Low Phase Noise (Pn)  Mm-wave  Multicore  Scalable Layout  Vco-core  
529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
Chen, P., Meng, X., Yin, J., Mak, P. I., Martins, R. P., Staszewski, R. B.. 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers.
Authors:  Chen, P.;  Meng, X.;  Yin, J.;  Mak, P. I.;  Martins, R. P.; et al.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
ADPLL  Bluetooth LE (BLE)  DCO  fractionalN PLL  phase noise (PN)  TDC  DTC  inverse-class-F  low power  the IoT