529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS

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Status	即將出版Forthcoming
	529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS
	Chen, P.; Meng, X.; Yin, J.; Mak, P. I.; Martins, R. P.; Staszewski, R. B.
Source Publication	IEEE Transactions on Circuits and Systems I: Regular Papers
ISSN	1549-8328
Abstract	This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed hybrid time-to-digital converter (TDC) extends the vernierTDC input range with little power overhead in order to overcome the stability issue in the conventional architectures. The hybrid TDC also facilitates a background gain calibration to achieve a stable in-band phase noise insensitive to process, voltage, and temperature (PVT) variations. The implementation of a buffercascaded DTC simplifies the design complexity of the fractional-N operation. The ADPLL also features a 200µW low-phase-noise inverse-class-F (class-F−1) digitally controlled oscillator (DCO) without the need of two-dimensional (2-D) capacitor tuning for frequency alignment of the fundamental and 2nd-harmonic. Fabricated in 65-nm CMOS, the ULP ADPLL prototype achieves 868 fsrms jitter in a fractional-N channel when consuming only 529µW, corresponding to a figure-of-merit (FoM) of −244 dB.
Keyword	ADPLL Bluetooth LE (BLE) DCO fractionalN PLL phase noise (PN) TDC DTC inverse-class-F low power the IoT
URL	View the original
Language	英語English
The Source to Article	PB_Publication
PUB ID	58947
Document Type	Journal article
Collection	University of Macau
Corresponding Author	Chen, P.
Recommended Citation GB/T 7714	Chen, P.,Meng, X.,Yin, J.,et al. 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers.
APA	Chen, P.., Meng, X.., Yin, J.., Mak, P. I.., Martins, R. P.., & Staszewski, R. B. 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers.
MLA	Chen, P.,et al."529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS".IEEE Transactions on Circuits and Systems I: Regular Papers .

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