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Deep learning assisted logic gates for real-time identification of natural tetracycline antibiotics Journal article
Tan, Ping, Chen, Yuhui, Chang, Hongrong, Liu, Tao, Wang, Jian, Lu, Zhiwei, Sun, Mengmeng, Su, Gehong, Wang, Yanying, Wang, Huimin David, Leung, Chunghang, Rao, Hanbing, Wu, Chun. Deep learning assisted logic gates for real-time identification of natural tetracycline antibiotics[J]. Food Chemistry, 2024, 454, 139705.
Authors:  Tan, Ping;  Chen, Yuhui;  Chang, Hongrong;  Liu, Tao;  Wang, Jian; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:8.5/8.2 | Submit date：2024/06/05
Deep Learning  Identification  Logic Gates  Smartphone  Tetracycline Antibiotics  
A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS Journal article
Lu, Xin, Wu, Jiangchao, Wang, Zhao, Xiang, Yifei, Liu, Liyuan, Mak, Pui In, Martins, Rui P., Law, Man Kay. A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(8), 3635 - 3639.
Authors:  Lu, Xin;  Wu, Jiangchao;  Wang, Zhao;  Xiang, Yifei;  Liu, Liyuan; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2024/05/16
Coarse-fine Conversion  Cyclic Time-to-digital Converter (Tdc)  Delays  Gated-ring Oscillator (Gro)  Generators  Image Edge Detection  Logic Gates  Phase Domain Reset  Ring Oscillators  Signal Resolution  Switches  
GDN-CMCF: A Gated Disentangled Network With Cross-Modality Consensus Fusion for Multimodal Named Entity Recognition Journal article
Huang, Guoheng, He, Qin, Dai, Zihao, Zhong, Guo, Yuan, Xiaochen, Pun, Chi Man. GDN-CMCF: A Gated Disentangled Network With Cross-Modality Consensus Fusion for Multimodal Named Entity Recognition[J]. IEEE Transactions on Computational Social Systems, 2023, 11(3), 3944-3954.
Authors:  Huang, Guoheng;  He, Qin;  Dai, Zihao;  Zhong, Guo;  Yuan, Xiaochen; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.5/4.6 | Submit date：2024/02/22
Common Space Learning  Correlation  Feature Disentanglement  Feature Extraction  Logic Gates  Multimodal Named Entity Recognition (Mner)  Semantics  Social Networking (Online)  Task Analysis  Visualization  
A 0.1-V VIN Subthreshold 3-Stage Dual-Branch Charge Pump with 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias Journal article
Yong, Jack Kee, Ramiah, Harikrishnan, Churchill, Kishore Kumar Pakkirisami, Chong, Gabriel, Mekhilef, Saad, Chen, Yong, Mak, Pui In, Martins, Rui P.. A 0.1-V VIN Subthreshold 3-Stage Dual-Branch Charge Pump with 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(9), 3929-3933.
Authors:  Yong, Jack Kee;  Ramiah, Harikrishnan;  Churchill, Kishore Kumar Pakkirisami;  Chong, Gabriel;  Mekhilef, Saad; et al.
Favorite | TC[WOS]:16 TC[Scopus]:17  IF:4.0/3.7 | Submit date：2022/08/05
Cmos  Control Systems  Cross-coupled Charge Pump (Cccp)  Energy Harvesting (Eh)  Logic Gates  Power Conversion Efficiency (Pce)  Switches  Switching Circuits  Transistors  Voltage  Voltage Control  
A 23-pW NMOS-Only Voltage Reference with Optimum Body Selection for Process Compensation Journal article
Kai Yu, Yangrun Zhou, Sizhen Li, Mo Huang. A 23-pW NMOS-Only Voltage Reference with Optimum Body Selection for Process Compensation[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(11), 4213-4217.
Authors:  Kai Yu;  Yangrun Zhou;  Sizhen Li;  Mo Huang
Favorite | TC[WOS]:9 TC[Scopus]:15  IF:4.0/3.7 | Submit date：2022/08/05
Fitting  Logic Gates  Mosfet  Nmos-only Voltage Reference  Optimum Body Selection  Power Demand  Process Compensation  Threshold Voltage  Transistors  Ultra-low-power  Voltage Measurement  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
Zhao, Xiaoteng, Chen, Yong, Mak, Pui In, Martins, Rui P.. A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 57(2), 546-561.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:4.6/5.6 | Submit date：2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
A 0.35-V 5,200-μm² 2.1-MHz Temperature- Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator Journal article
Ka-Meng Lei, Pui-In Mak, Rui P. Martins. A 0.35-V 5,200-μm² 2.1-MHz Temperature- Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator[J]. IEEE Journal of Solid-State Circuits, 2021, 56(9), 2701 - 2710.
Authors:  Ka-Meng Lei;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:21 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2021/09/20
Asymmetric Rc Network  Circuit Stability  Cmos  Energy-harvesting  Internet-of-things (Iot)  Logic Gates  Mos Devices  Oscillators  Relaxation Oscillator (Rxo)  Resilience  Stability Criteria  Swing-boosting  Temperature Resilience  Thermal Stability  Ultra-low-power  Ultra-low-voltage (Ulv).  
Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications Conference paper
Chio-In Ieong, Mingzhong Li, Man-Kay Law, Pui-In Mak, Mang-I Vai, Peng-Un Mak, Feng Wan, Rui P. Martins. Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2013.
Authors:  Chio-In Ieong;  Mingzhong Li;  Man-Kay Law;  Pui-In Mak;  Mang-I Vai; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4 | Submit date：2018/12/24
Transistors  Capacitances  Libraries  Logic Gates  Very Large Scale Integration  Power Demand  Inverter