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A 0.1-V VIN Subthreshold 3-Stage Dual-Branch Charge Pump with 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias | |
Yong, Jack Kee1; Ramiah, Harikrishnan1; Churchill, Kishore Kumar Pakkirisami1; Chong, Gabriel1,5; Mekhilef, Saad2; Chen, Yong3; Mak, Pui In3; Martins, Rui P.3,4 | |
2022-09 | |
Source Publication | IEEE Transactions on Circuits and Systems II: Express Briefs |
ISSN | 1549-7747 |
Volume | 69Issue:9Pages:3929-3933 |
Abstract | This Brief proposes a 3-stage dual-branch charge pump (CP) with an advanced dynamic gate-biasing technique (DGB) enabling ultra-low-voltage (0.1 V) energy harvesting. Specifically, we reduce the forward conduction loss and the reverse current leakage loss with the combination of an advanced DGB and an NMOS-PMOS dual-switch transistor pair. Also, we investigate the relationship between the pumping capacitance and the power conversion efficiency (PCE) of the CP, thus guiding the PCE improvement with minimal capacitance. The prototype fabricated in 65-nm CMOS achieves a 43.4% PCE at a 0.1-V input voltage. |
Keyword | Cmos Control Systems Cross-coupled Charge Pump (Cccp) Energy Harvesting (Eh) Logic Gates Power Conversion Efficiency (Pce) Switches Switching Circuits Transistors Voltage Voltage Control |
DOI | 10.1109/TCSII.2022.3182344 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000848263100065 |
Scopus ID | 2-s2.0-85132694651 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS |
Corresponding Author | Ramiah, Harikrishnan |
Affiliation | 1.Department of Electrical Engineering, Faculty of Engineering, University of Malaya, Kuala Lumpur, Malaysia 2.School of Science, Computing and Engineering Technologies, Swinburne University of Technology, Australia 3.State-Key Laboratory of Analog and Mixed-Signal VLSI-IME/DECE-FST, University of Macau, Macao, China 4.Instituto Superior Técnico, Universidade de Lisboa, 1649-004 Lisbon, Portugal 5.Analog & Logic ICs Department, Nexperia R&D Penang, Bayan Lepas 11900, Malaysia |
Recommended Citation GB/T 7714 | Yong, Jack Kee,Ramiah, Harikrishnan,Churchill, Kishore Kumar Pakkirisami,et al. A 0.1-V VIN Subthreshold 3-Stage Dual-Branch Charge Pump with 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(9), 3929-3933. |
APA | Yong, Jack Kee., Ramiah, Harikrishnan., Churchill, Kishore Kumar Pakkirisami., Chong, Gabriel., Mekhilef, Saad., Chen, Yong., Mak, Pui In., & Martins, Rui P. (2022). A 0.1-V VIN Subthreshold 3-Stage Dual-Branch Charge Pump with 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias. IEEE Transactions on Circuits and Systems II: Express Briefs, 69(9), 3929-3933. |
MLA | Yong, Jack Kee,et al."A 0.1-V VIN Subthreshold 3-Stage Dual-Branch Charge Pump with 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias".IEEE Transactions on Circuits and Systems II: Express Briefs 69.9(2022):3929-3933. |
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