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Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
Liu, Yueduo, Bao, Rongxin, Zhu, Zihao, Yang, Shiheng, Zhou, Xiong, Li, Qiang, Yin, Jun, Mak, Pui In. Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(2), 495-505.
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2022/03/04
Voltage-controlled Oscillators  Jitter  Clocks  Phase Noise (Pn)  Topology  Performance Evaluation  Delays  Figure Of Merit (Fom)  Injection-locked Clock Multiplier (Ilcm)  Multiplying Delay-locked Loop (Mdll)  Power  Ring Voltage-controlled Oscillator (Rvco)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
Shiheng Yang, Jun Yin, Pui-In Mak, Rui P. Martins. A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs[J]. IEEE Journal of Solid-State Circuits, 2019, 54(1), 88-98.
Authors:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs Journal article
Yang, S., Yin, J., Mak, P. I., Martins, R. P.. A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 88-98.
Authors:  Yang, S.;  Yin, J.;  Mak, P. I.;  Martins, R. P.
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2022/01/24
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 0.05-to-10GHz, 19-to-22GHz, and 38-to-44GHz Frequency Synthesizer for Software-Defined Radios in 0.13-um CMOS Process Journal article
Rong, S., Yin, J., Luong, H.. A 0.05-to-10GHz, 19-to-22GHz, and 38-to-44GHz Frequency Synthesizer for Software-Defined Radios in 0.13-um CMOS Process[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2016, 109-113.
Authors:  Rong, S.;  Yin, J.;  Luong, H.
Favorite |   IF:4.0/3.7 | Submit date：2022/08/19
Frequency synthesizer  soft-ware defined radio  SDR  UWB  fast hopping  mm-Wave  dual band  voltagecontrolled oscillator  injection-locked frequency multiplier  injection-locked oscillator  sub-harmonic injection  
A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz frequency synthesizer for software-defined radios in 0.13-μm CMOS process Journal article
Rong S., Yin J., Luong H.C.. A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz frequency synthesizer for software-defined radios in 0.13-μm CMOS process[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2016, 63(1), 109-113.
Authors:  Rong S.;  Yin J.;  Luong H.C.
Favorite | TC[WOS]:22 TC[Scopus]:27 | Submit date：2019/02/14
Dual Band  Fast Hopping  Frequency Synthesizer  Injection-locked Frequency Multiplier  Injection-locked Oscillator  Mm-wave  Sdr  Soft-ware Defined Radio  Sub-harmonic Injection  Uwb  Voltage Controlled Oscillator