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A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array Journal article
Dong, Li, Song, Yan, Xie, Yi, Xin, Youze, Li, Ken, Jing, Xixin, Zhang, Bing, Gui, Xiaoyan, Geng, Li. A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array[J]. Microelectronics Journal, 2021, 113, 105109.
Authors:  Dong, Li;  Song, Yan;  Xie, Yi;  Xin, Youze;  Li, Ken; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.9/1.7 | Submit date：2021/12/08
Analog-to-digital Converter (Adc)  Area-efficient  Dac Mismatch  High Linearity  Insensitive Geometry  
A 1-V 4-mW Differential-Folded Mixer with Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF Journal article
Vitee,Nandini, Ramiah,Harikrishnan, Mak,Pui In, Yin,Jun, Martins,Rui P.. A 1-V 4-mW Differential-Folded Mixer with Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020, 28(5), 1164-1174.
Authors:  Vitee,Nandini;  Ramiah,Harikrishnan;  Mak,Pui In;  Yin,Jun;  Martins,Rui P.
Favorite | TC[WOS]:5 TC[Scopus]:5  IF:2.8/2.8 | Submit date：2021/03/04
Capacitive Feedback  Cmos  High Linearity  Mixer  Positive Feedback  Third-order Intercept Point (Iip3)  Third-order Intermodulation (Im3) Cancellation  
A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer with Integrated Transformer-Based Gate Inductor and IM2 Injection Technique Journal article
Vitee,Nandini, Ramiah,Harikrishnan, Mak,Pui In, Yin,Jun, Martins,Rui P.. A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer with Integrated Transformer-Based Gate Inductor and IM2 Injection Technique[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020, 28(3), 700-713.
Authors:  Vitee,Nandini;  Ramiah,Harikrishnan;  Mak,Pui In;  Yin,Jun;  Martins,Rui P.
Favorite | TC[WOS]:15 TC[Scopus]:25  IF:2.8/2.8 | Submit date：2021/03/04
Balun-low-noise Amplifier (Lna) Mixer  Cmos  High Linearity  Inductively Source Degeneration Transconductor  Low-power  Second-order Intermodulation (Im2) Injection  Third-order Input Intercept Point (Iip3)  Volterra Series  
A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin, S. W., U, S.P., Maloberti, F., Martins, R. P.. A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI), 2019, 1161-1172.
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter  Iadc  Incremental Adc  Sigma-delta  Linear  Exponential  Accumulation  Two-phase  Multi-bit  Mismatch Error  Dynamic Element Matching (Dem)  Data Weighting Average (Dwa)  High Linearity  Notch  
A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin,Sai Weng, Seng-Pan,S. P.U., Maloberti,Franco, Martins,Rui P.. A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2019, 54(4), 1161-1172.
Authors:  Wang, B.;  Sin,Sai Weng;  Seng-Pan,S. P.U.;  Maloberti,Franco;  Martins,Rui P.
Favorite | TC[WOS]:44 TC[Scopus]:55  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Data Weighting Average  Dynamic Element Matching (Dem)  High Linearity  Incremental Adc (iAdc)  Linear-exponential Accumulation  Mismatch Error  Multi-bit  Notch  Sigma Delta  Two Phase