This paper presents an effective method to arrange high linearity and area-efficient digital-to-analog converter (DAC) to enhance the resolution of successive approximation register (SAR) analog-to-digital converter (ADC). The relationship between ENOB and DAC mismatch error is theoretically analyzed, which gives the guidance of optimizing the mismatch error of DAC array. The parasitic effect on the linearity of DAC can be obtained through a normalized parasitic capacitor model, which evaluates the parasitic capacitors caused by the layout and routing of DAC array. A 10-bit 20 MS/s SAR ADC with redundancy is fabricated with 0.18 μm CMOS process. Measurement results show that the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) are 57.9 dB and 75.9 dB, respectively. The SAR ADC achieves a Walden FoM (FoM) of 75.1 fJ/conversion step and occupies a small active area of 0.069 mm benefited from the compact layout.