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Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects Journal article
He, Jian, Lu, Donglai, Xue, Haiyun, Chen, Sikai, Liu, Han, Li, Leliang, Li, Guike, Zhang, Zhao, Liu, Jian, Liu, Liyuan, Wu, Nanjian, Yu, Ningmei, Liu, Fengman, Xiao, Xi, Chen, Yong, Qi, Nan. Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(11), 4345-4357.
Authors:  He, Jian;  Lu, Donglai;  Xue, Haiyun;  Chen, Sikai;  Liu, Han; et al.
Favorite | TC[WOS]:17 TC[Scopus]:20  IF:5.2/4.5 | Submit date：2022/08/05
400gbase-sr8  Continuous-time Linear Equalizer (Ctle)  Four-level Pulse Amplitude Modulation (Pam-4)  Integrated Circuit Modeling  Nonlinear Optics  Optical Receivers  Optical Superlattices  Optical Transmitters  Sige Bicmos  Trans-impedance Amplifier (Tia)  Transceiver (Trx)  Transceivers  Vertical Cavity Surface Emitting Lasers  Vertical-cavity-surface-emitting Laser (Vcsel) Driver  
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR Journal article
Liao, Qiwen, Zhang, Yuguang, Ma, Siyuan, Wang, Lei, Li, Leliang, Li, Guike, Zhang, Zhao, Liu, Jian, Wu, Nanjian, Liu, Liyuan, Chen, Yong, Xiao, Xi, Qi, Nan. A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR[J]. IEEE Journal of Solid-State Circuits, 2022, 57(3), 767-780.
Authors:  Liao, Qiwen;  Zhang, Yuguang;  Ma, Siyuan;  Wang, Lei;  Li, Leliang; et al.
Favorite | TC[WOS]:23 TC[Scopus]:30  IF:4.6/5.6 | Submit date：2022/03/28
Clock And Data Recovery (Cdr)  Cmos  Distributed Driver  Four-level Pulse Amplitude (Pam-4)  Machâ Zehnder Modulator (Mzm)  Optical Digital-to-analog Converter (Dac)  Silicon Photonic (Siph)  Transmitter (Tx)  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
Zhao, Xiaoteng, Chen, Yong, Mak, Pui In, Martins, Rui P.. A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 57(2), 546-561.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:4.6/5.6 | Submit date：2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects Conference paper
Lu, Donglai, He, Jian, Li, Weizhong, Chen, Sikai, Liu, Jian, Wu, Nanjian, Yu, Ningmei, Liu, Liyuan, Chen, Yong, Xiao, Xi, Qi, Nan. 100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021, 253-256.
Authors:  Lu, Donglai;  He, Jian;  Li, Weizhong;  Chen, Sikai;  Liu, Jian; et al.
Favorite | TC[WOS]:5 TC[Scopus]:4 | Submit date：2022/05/13
400gbase-sr8  Four-level Pulse Amplitude Modulation (Pam-4)  Trans-impedance Amplifier (Tia)  Vertical-cavity-surface-emitting Laser (Vcsel) Driver  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS Journal article
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(1), 89-102.
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:21 TC[Scopus]:21  IF:5.2/4.5 | Submit date：2021/03/09
Bang- Bang Clock And Data Recovery (Bbcdr)  Bang-bang Phase Detector (Bbpd)  Cmos  Four- And Eight-level Pulse Amplitude Modulation (Pam-4/-8)  Half Rate  Hogge And alexAnder Pd  Jitter Tolerance (Jtol).  Jitter Transfer Function (Jtf)  Non-return-to-zero (Nrz)  Strongarm Comparator  
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS Journal article
Fan,Chao, Yu,Wei Han, Mak,Pui In, Martins,Rui P.. A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(12), 4850-4861.
Authors:  Fan,Chao;  Yu,Wei Han;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:9 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2021/03/09
Cmos  Current-mode-logic (Cml) Driver  Feed-forward Equalization (Ffe)  Four-level Pulse-amplitude Modulation (Pam-4)  Source-series-terminated (Sst) Driver  Sst-cml-hybrid (Sch) Driver  Transmitter (Tx)