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A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization Journal article
Li, Jixuan, Li, Ke, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Li, Jixuan;  Li, Ke;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/26
Convolutional Neural Network (Cnn)  Digital Signal Processing (Dsp)  Field-programmable Gate Array (Fpga)  Processing Unit (Pe) Utilization  Residual Block  
An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications Journal article
Cao, Rujian, Zhao, Zhongyu, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II-Express Briefs, 2024, 71(11), 4688-4692.
Authors:  Cao, Rujian;  Zhao, Zhongyu;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/10/10
Sparse Matrices  Computational Modeling  Transformers  Hardware  Energy Efficiency  Circuits  Throughput  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Sparsity  Transformer  
Modeling Attack Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability Journal article
Xu, Chongyao, Zhang, Litao, Law, Man Kay, Zhao, Xiaojin, Mak, Pui In, Martins, Rui P.. Modeling Attack Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability[J]. IEEE Internet of Things Journal, 2023, 10(18), 16300 - 16315.
Authors:  Xu, Chongyao;  Zhang, Litao;  Law, Man Kay;  Zhao, Xiaojin;  Mak, Pui In; et al.
Favorite | TC[WOS]:11 TC[Scopus]:16  IF:8.2/9.0 | Submit date：2023/08/03
Field-programmable Gate Array (Fpga)  Machine Learning (Ml) Modeling Attack  Obfuscated Interconnection (Oi)  Physical Unclonable Function (Puf)  
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications Journal article
Zhao, Zhongyu, Cao, Rujian, Un, Ka Fai, Yu, Wei Han, Mak, Pui In, Martins, Rui P.. An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(1), 281-285.
Authors:  Zhao, Zhongyu;  Cao, Rujian;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In; et al.
Favorite | TC[WOS]:13 TC[Scopus]:15  IF:4.0/3.7 | Submit date：2022/08/08
Transformers  Energy Efficiency  Broadcasting  Convolutional Neural Networks  Integrated Circuit Modeling  Field Programmable Gate Arrays  Random Access Memory  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Energy Efficiency  Image Recognition  Transformer  
Transfer-Path-Based Hardware-Reuse Strong PUF Achieving Modeling Attack Resilience With >200 Million Training CRPs Journal article
Xu, Chongyao, Zhang, Jieyun, Law, Man-Kay, Zhao, Xiaojin, Mak, Pui-In, Martins, Rui P.. Transfer-Path-Based Hardware-Reuse Strong PUF Achieving Modeling Attack Resilience With >200 Million Training CRPs[J]. IEEE Transactions on Information Forensics and Security, 2023, 18, 2188 - 2203.
Authors:  Xu, Chongyao;  Zhang, Jieyun;  Law, Man-Kay;  Zhao, Xiaojin;  Mak, Pui-In; et al.
Favorite | TC[WOS]:4 TC[Scopus]:6  IF:6.3/7.3 | Submit date：2023/03/29
Field-programmable Gate Array (Fpga)  Hardware Reuse  Machine Learning (Ml) Attack  Multiplier  Physical Unclonable Function (Puf)  Response Stream (Rs)  Transfer Path (Tp)  
An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition Journal article
Lei Xuan, Ka-Fai Un, Chi-Seng Lam, Rui P. Martins. An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(10), 4003-4007.
Authors:  ; et al.
Favorite | TC[WOS]:30 TC[Scopus]:32  IF:4.0/3.7 | Submit date：2022/06/14
Frequency Modulation  Field Programmable Gate Arrays  Energy Efficiency  Memory Management  Random Access Memory  Arrays  Computational Cost  Convolutional Neural Network (Cnn)  Field-programmable Gate Array (Fpga)  Mobilenetv2  Neural Network  Quantization  
A Task-Parallel and Reconfigurable FPGA-Based Hardware Implementation of Extreme Learning Machine Conference paper
Huang, Hui, Rong, Hai Jun, Yang, Zhao Xu. A Task-Parallel and Reconfigurable FPGA-Based Hardware Implementation of Extreme Learning Machine[C]:Association for Computing Machinery, 2022, 194-202.
Authors:  Huang, Hui;  Rong, Hai Jun;  Yang, Zhao Xu
Favorite | TC[Scopus]:1 | Submit date：2022/05/17
Extreme Learning Machine  Field-programmable Gate Array  Reconfigurable Architecture  Task-parallel Computing  
A high-performance, hardware-based deep learning system for disease diagnosis Journal article
Siddique, Ali, Iqbal, Muhammad Azhar, Aleem, Muhammad, Lin, Jerry Chun Wei. A high-performance, hardware-based deep learning system for disease diagnosis[J]. PeerJ Computer Science, 2022, 8, 17.
Authors:  Siddique, Ali;  Iqbal, Muhammad Azhar;  Aleem, Muhammad;  Lin, Jerry Chun Wei
Favorite | TC[Scopus]:2  IF:3.5/3.4 | Submit date：2023/01/30
Activation Function  Cancer Diagnosis  Deep Learning  Field Programmable Gate Array  Hardware Friendly  Neural Networks  Swish  
Modular chaotification model with FPGA implementation Journal article
Hua, Zhongyun, Zhou, Binghang, Zhang, Yinxing, Zhou, Yicong. Modular chaotification model with FPGA implementation[J]. Science China Technological Sciences, 2021, 64(7), 1472-1484.
Authors:  Hua, Zhongyun;  Zhou, Binghang;  Zhang, Yinxing;  Zhou, Yicong
Favorite | TC[WOS]:10 TC[Scopus]:10  IF:4.4/4.3 | Submit date：2021/12/08
Chaotic System  Field-programmable Gate Array (Fpga)  Hardware Implementation  Nonlinear System  Pseudorandom Number Generator (Prng)  
Sine Chaotification Model for Enhancing Chaos and Its Hardware Implementation Journal article
Hua, Zhongyun, Zhou, Binghang, Zhou, Yicong. Sine Chaotification Model for Enhancing Chaos and Its Hardware Implementation[J]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2019, 66(2), 1273-1284.
Authors:  Hua, Zhongyun;  Zhou, Binghang;  Zhou, Yicong
Favorite | TC[WOS]:186 TC[Scopus]:209  IF:7.5/8.0 | Submit date：2018/10/30
Chaotic System  Chaotification  Chaos-based Application  Cryptography  Field-programmable Gate Array (Fpga) Implementation  Nonlinear Control