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An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications
Zhao, Zhongyu1; Cao, Rujian1; Un, Ka Fai1; Yu, Wei Han1; Mak, Pui In1; Martins, Rui P.1,2
2023-01
Source PublicationIEEE Transactions on Circuits and Systems II: Express Briefs
ISSN1549-7747
Volume70Issue:1Pages:281-285
Abstract

The transformer-based model has great potential to deliver higher accuracy for object recognition applications when comparing it with the convolution neural network (CNN). Yet, the amount of weight sharing of a transformer-based model is significantly lower than that of the CNN, which should apply different dataflow to reduce the memory access. This brief proposes a transformer accelerator with an output block stationary (OBS) dataflow to minimize the repeated memory access by block-level and vector-level broadcasting while preserving a high digital signal processor (DSP) utilization rate, leading to higher energy efficiency. It also lowers the memory access bandwidth to the input and output. Verified through an FPGA, the proposed accelerator evaluates a transformer-in-transformer (TNT) model with a throughput of 728.3 GOPs, corresponding to energy efficiency of 58.31 GOPs/W.

KeywordTransformers Energy Efficiency Broadcasting Convolutional Neural Networks Integrated Circuit Modeling Field Programmable Gate Arrays Random Access Memory Dataflow Digital Accelerator Energy-efficient Field-programmable Gate Array (Fpga) Energy Efficiency Image Recognition Transformer
DOI10.1109/TCSII.2022.3196055
URLView the original
Indexed BySCIE
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000908711600057
PublisherInstitute of Electrical and Electronics Engineers Inc.
Scopus ID2-s2.0-85135759988
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Citation statistics
Document TypeJournal article
CollectionTHE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)
Faculty of Science and Technology
INSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorUn, Ka Fai
Affiliation1.University of Macau, State-Key Laboratory of Analog and Mixed-Signal Vlsi, Institute of Microelectronics, The Faculty of Science and Technology-ECE, Macau, Macao
2.Instituto Superior Técnico, Universidade de Lisboa, Lisbon, 1649-004, Portugal
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Zhao, Zhongyu,Cao, Rujian,Un, Ka Fai,et al. An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(1), 281-285.
APA Zhao, Zhongyu., Cao, Rujian., Un, Ka Fai., Yu, Wei Han., Mak, Pui In., & Martins, Rui P. (2023). An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 70(1), 281-285.
MLA Zhao, Zhongyu,et al."An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications".IEEE Transactions on Circuits and Systems II: Express Briefs 70.1(2023):281-285.
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