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A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects Conference paper
Ming Zhong, Qingwen Wang, Yong Chen, Jian Liu, Liyuan Liu, Xinghua Wang, Xiaoming Xiong, Nan Qi. A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects[C]:IEEE, 2021, 255-256.
Authors:  Ming Zhong;  Qingwen Wang;  Yong Chen;  Jian Liu;  Liyuan Liu; et al.
Favorite | TC[Scopus]:7 | Submit date：2022/05/13
Clock And Data Recovery (Cdr)  Driver  Equalization  Serializer  Source-series-terminated (Sst)  
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS Journal article
Fan,Chao, Yu,Wei Han, Mak,Pui In, Martins,Rui P.. A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(12), 4850-4861.
Authors:  Fan,Chao;  Yu,Wei Han;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:9 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2021/03/09
Cmos  Current-mode-logic (Cml) Driver  Feed-forward Equalization (Ffe)  Four-level Pulse-amplitude Modulation (Pam-4)  Source-series-terminated (Sst) Driver  Sst-cml-hybrid (Sch) Driver  Transmitter (Tx)  
A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS Conference paper
Arya Balachandran, Yong Chen, Chirn Chye Boon. A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS[C]:IEEE, 2019, 221-224.
Authors:  Arya Balachandran;  Yong Chen;  Chirn Chye Boon
Favorite | TC[Scopus]:17 | Submit date：2021/10/28
Cmos  Analog Front-end (Afe)  Low Frequency Equalization (Lfeq)  Inductorless  Continuous-time Linear Equalizer (Ctle)  Inductorless  Channel Loss  Decision Feedback Equalization (Dfe)  Receiver  
A 0.013-mm(2) 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS Journal article
Balachandran, Arya, Chen, Yong, Boon, Chirn Chye. A 0.013-mm(2) 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26(3), 599-603.
Authors:  Balachandran, Arya;  Chen, Yong;  Boon, Chirn Chye
Favorite | TC[WOS]:16 TC[Scopus]:18  IF:2.8/2.8 | Submit date：2018/10/30
Channel Loss  Cmos Equalizer  Continuous-time Linear Equalizer (Ctle)  Figure Of Merit (Fom)  Inductorless  Intersymbol Interference (Isi)  Low-frequency Equalization (Lfeq)  
A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer under 21-dB Channel Loss in 65-nm CMOS Journal article
Balachandran A., Chen Y., Boon C.C.. A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer under 21-dB Channel Loss in 65-nm CMOS[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 26(3), 599-603.
Authors:  Balachandran A.;  Chen Y.;  Boon C.C.
Favorite | TC[WOS]:16 TC[Scopus]:18 | Submit date：2019/02/14
Channel Loss  Cmos Equalizer  Continuoustime Linear Equalizer (Ctle)  Figure Of Merit (Fom)  Inductorless  Intersymbol Interference (Isi)  Low-frequency Equalization (Lfeq)  
A 0.002-mm2 6.4-mW 10-Gb/s full-rate direct DFE receiver with 59.6%horizontal eye opening under 23.3-db channel loss at nyquist frequency Journal article
Yong Chen, Pui-In Mak, Li Zhang, Yan Wang. A 0.002-mm2 6.4-mW 10-Gb/s full-rate direct DFE receiver with 59.6%horizontal eye opening under 23.3-db channel loss at nyquist frequency[J]. IEEE Transactions on Microwave Theory and Techniques, 2014, 62(12), 3107-3117.
Authors:  Yong Chen;  Pui-In Mak;  Li Zhang;  Yan Wang
Favorite | TC[WOS]:19 TC[Scopus]:23  IF:4.1/4.2 | Submit date：2019/02/12
Active Inductor (Ai)  Analog One-tap Nonreturn-to-zero (Nrz) Feedback  Bathtub Curve  Bit Error Rate (Ber)  Channel Loss  Clocked-one-tap Return-to-zero (Rz) Feedback  Cmos  Decision Feedback Equalization (Dfe) Receiver  Horizontal Eye Opening  Pseudorandom Binary Sequence (Prbs)  Vertical Eye Opening  
Efficient Depth Peeling via Bucket Sort Conference paper
Liu, Fang, Huang, Meng-Cheng, Liu, Xue-Hui, Wu, En-Hua. Efficient Depth Peeling via Bucket Sort[C]. Association for Computing Machinery, 2009, 51-58.
Authors:  Liu, Fang;  Huang, Meng-Cheng;  Liu, Xue-Hui;  Wu, En-Hua
Favorite | TC[Scopus]:42 | Submit date：2018/11/06
Graphics Hardware  Depth Peeling  Multiple Render Target (Mrt)  Bucket Sort  Order Independent Transparency (Oit)  Max/min Blending  Histogram Equalization