This paper presents a four-channel voltage-mode serializer in 40-nm CMOS for network interface card (NIC) optical interconnects. Each channel is designed by a quarter-rate clock and data recovery (CDR) with digital loop filter, which recovers the data received by analog front-end circuits. A source-series-terminated (SST) driver employs three groups of slices in parallel to achieve multi-tap configurable equalization. A shared phase-locked loop is integrated to provide a 25-GHz global clock for all the channels. The serializer works from 1-V supply with 163 mW power when the CDR is enabled, and consumes 36.2 mW in the pseudo-random bit sequence (PRBS) testing mode. The post-layout simulation results show clean output eye diagrams at 25-Gb/s datarate. The differential output swing reaches 1.07 Vppd and the jitter is less than 2.5 ps.