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A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
Jiang, Dongyang, Qi, Liang, Sin, Sai Weng, Maloberti, Franco, Martins, Rui P.. A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56(8), 2375-2387.
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:14  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
A 4.2mW 77.1dB-SNDR 5MHz-BW DT 2-1 MASH ΔΣ Modulator with Multirate Opamp Sharing Journal article
Qi, L., Sin, W., U, S.P., Maloberti, F., Martins, R. P.. A 4.2mW 77.1dB-SNDR 5MHz-BW DT 2-1 MASH ΔΣ Modulator with Multirate Opamp Sharing[J]. IEEE Transactions on Circuits and Systems I - Regular Papers, 2017, 2641-2654.
Authors:  Qi, L.;  Sin, W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/24
Analog-to-digital Converter (Adc)  Discrete-time (Dt) Delta Sigma (Δς) Modulator  Multi-stage Noise Shaping (Mash)  Wideband  Power-efficient  Opamp Sharing  Multirate  Sar Quantizer  
A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing Journal article
Liang Qi, Sai-Weng Sin, Seng-Pan, U., Franco Maloberti, Rui Paulo Martins. A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64(10), 2641-2654.
Authors:  Liang Qi;  Sai-Weng Sin;  Seng-Pan, U.;  Franco Maloberti;  Rui Paulo Martins
Favorite | TC[WOS]:35 TC[Scopus]:44  IF:5.2/4.5 | Submit date：2018/10/30
Analog-to-digital Converter (Adc)  Discrete-time (Dt) Delta Sigma (Delta Sigma) Modulator  Multi-stage Noise Shaping (Mash)  Wideband  Power-efficient  Opamp Sharing  Multirate  Successive Approximation Register (Sar) Quantizer  
Active–Passive ΔΣ Modulator for High-Resolution and Low-Power Applications Journal article
Hussain, A., Sin, S. W., Chan, C. H., U, S.P., Maloberti, F., Martins, R. P.. Active–Passive ΔΣ Modulator for High-Resolution and Low-Power Applications[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 364-374.
Authors:  Hussain, A.;  Sin, S. W.;  Chan, C. H.;  U, S.P.;  Maloberti, F.; et al.
Favorite |   IF:2.8/2.8 | Submit date：2022/01/24
Delta-sigma Modulator ( m)  Discrete Time (Dt)  Low-gain-amplifier-based Switched-capacitor (Sc) Integrator  Noise Shaping  Passive Sc Integrator  
Active-Passive Delta Sigma Modulator for High-Resolution and Low-Power Applications Journal article
Hussain, Arshad, Sin, Sai-Weng, Chan, Chi-Hang, U, Seng-Pan (Ben), Maloberti, Franco, Martins, Rui P.. Active-Passive Delta Sigma Modulator for High-Resolution and Low-Power Applications[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25(1), 364-374.
Authors:  Hussain, Arshad;  Sin, Sai-Weng;  Chan, Chi-Hang;  U, Seng-Pan (Ben);  Maloberti, Franco; et al.
Favorite | TC[WOS]:21 TC[Scopus]:23  IF:2.8/2.8 | Submit date：2018/10/30
Delta-Sigma Modulator (Delta Sigma m)  Discrete Time (Dt)  Low-gain-amplifier-based Switched-capacitor (Sc) Integrator  Noise Shaping  Passive Sc Integrator