This paper presents a discrete time 2-1 MASH Delta-Sigma (Delta Sigma) modulator with multirate opamp sharing for analog-to-digital converters, targeting the optimization of power efficiency in active blocks, such as opamps and quantizers. Through the allocation of different settling times to the opamps and by adopting the multirate technique, the power of the shared opamps is utilized more efficiently, and the 4-b successive approximation register quantizer and the data weighted averaging block in the first stage enjoy additional operation time. Moreover, a detailed analysis and related simulations are presented to validate the enhanced opamp power efficiency in the proposed sharing scheme. The 65-nm CMOS experimental chip running at multirate 120/240 MHz achieves a mean signal-tonoise and distortion ratio (SNDR) of 77.1 dB for a 5-MHz bandwidth, consuming 4.2 mW from a 1.2 V supply and occupying 0.066-mm(2) core area. It exhibits a Walden figure of merit (FoM) of 69.7 fJ/conv-step and a Schreier FoM of 167.9 dB based on SNDR.