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A Data-Driven Finite-State Machine-Based Control for Hybrid Parallel Multiconverters: Fusion Topology for High-Power Applications Journal article
Pang,Ying, Bai,Ziyi, Xiang,Zeng, Wang,Lei, Wong,Chi Kong, Lam,Chi Seng, Ma,Fujun, Che,Liang, Wong,Man Chung. A Data-Driven Finite-State Machine-Based Control for Hybrid Parallel Multiconverters: Fusion Topology for High-Power Applications[J]. IEEE Transactions on Industrial Electronics, 2023, 70(12), 11853-11864.
Authors:  Pang,Ying;  Bai,Ziyi;  Xiang,Zeng;  Wang,Lei;  Wong,Chi Kong; et al.
Favorite | TC[WOS]:1 TC[Scopus]:3  IF:7.5/8.0 | Submit date：2023/08/03
Data-driven Control  High Power  Multiconverter  Power Quality  Voltage Source Converter (Vsc)  
A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator Journal article
Zhang, Hongshuai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3565-3575.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:4.6/5.6 | Submit date：2024/01/02
Analog-to-digital Converter (Adc)  Auxiliary Noise Shaping (Ns) Successive-approximation Register (Sar) Adc  Capacitor Stacking  Data-weighted Averaging And detect-And-skip (Dwa And Das)  Differential Sampling  Energy Efficient  Error SupprEssion (Es) And Reconstruction  Gain Error Shaping (Ges)  Partial Time Interleaving  Passive Ns  Pipelined Sar  Quantization Predication Unrolled  Two-step Floating Inverter Amplifier (Fia)  
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation Journal article
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhou, Xionghui, Han, Mei, Stefano, Crovetti Paolo, Mak, Pui In, Martins, Rui P.. A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation[J]. International Journal of Circuit Theory and Applications, 2023, 51(5), 1988-2015.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhou, Xionghui;  Han, Mei; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:1.8/1.7 | Submit date：2023/06/05
Bang-bang Clock And Data Recovery (Bbcdr)  Current Mismatch  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Phase Interpolator (Pi)  R-2r Digital-to-analog Converter (Dac)  Ring Oscillator (Ro)  Switched-capacitor (Sc) Array  Wide Capture Range  
A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling Conference paper
Wang, Qingxun, Pan, Yuhan, Chen, Kaiquan, Lin, Yu, Wang, Biao, Qi, Liang. A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling[C]:IEEE345 E 47TH ST, NEW YORK, NY 10017 USA, 2023.
Authors:  Wang, Qingxun;  Pan, Yuhan;  Chen, Kaiquan;  Lin, Yu;  Wang, Biao; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2024/02/23
Incremental Analog-to-digital Converter (Iadc)  Linear-exponential  Second-order Noise Coupling (Nc)  The Effective Data Weighting Averaging (Dwa) And Suppression Of Thermal Noise  
A 880 nW, 100 kS/s, 13 bit Differential Relaxation-DAC in 180 nm Conference paper
Rubino,Roberto, Musolino,Francesco, Chen,Yong, Richelli,Anna, Crovetti,Paolo. A 880 nW, 100 kS/s, 13 bit Differential Relaxation-DAC in 180 nm[C]. Bosch, et al., Huawei, Photeon Technologies, Synopsys:Institute of Electrical and Electronics Engineers Inc., 2023, 269-272.
Authors:  Rubino,Roberto;  Musolino,Francesco;  Chen,Yong;  Richelli,Anna;  Crovetti,Paolo
Favorite | TC[WOS]:3 TC[Scopus]:3 | Submit date：2023/08/03
Consumer Data Converter.  D/a Converter (Dac)  Digital Intensive  Relaxation D/a Converter (Redac)  Ultra-low Area  Ultra-low Power  
L: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs Journal article
Wang, Bo, Law, Man Kay, Schneider, Jens. L: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs[J]. IEEE Transactions on Signal Processing, 2023, 71, 3229-3241.
Authors:  Wang, Bo;  Law, Man Kay;  Schneider, Jens
Favorite | TC[WOS]:2 TC[Scopus]:1  IF:4.6/5.2 | Submit date：2024/02/22
Analog-to-digital Data Converter  Digital Linear Filter  Frequency Notch  Incremental Delta-sigma Adc  l  Reconstruction Filter  Thermal Noise Penalty  
A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector Conference paper
Ge, Xinyi, Chen, Yong, Wang, Lin, Qi, Nan, Mak, Pui In, Martins, Rui P.. A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2022.
Authors:  Ge, Xinyi;  Chen, Yong;  Wang, Lin;  Qi, Nan;  Mak, Pui In; et al.
Favorite | TC[WOS]:4 TC[Scopus]:5 | Submit date：2023/01/30
Bang-bang Phase Detector (Bbpd)  Charge Steering  Clock And Data Recovery (Cdr)  Cmos  Half Rate  Non- Return-to-zero (Nrz)  Quadrature Voltage-controlled Oscillator (Qvco)  Return-to-zero (Rz)  Rz-to-nrz Converter  
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR Journal article
Liao, Qiwen, Zhang, Yuguang, Ma, Siyuan, Wang, Lei, Li, Leliang, Li, Guike, Zhang, Zhao, Liu, Jian, Wu, Nanjian, Liu, Liyuan, Chen, Yong, Xiao, Xi, Qi, Nan. A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR[J]. IEEE Journal of Solid-State Circuits, 2022, 57(3), 767-780.
Authors:  Liao, Qiwen;  Zhang, Yuguang;  Ma, Siyuan;  Wang, Lei;  Li, Leliang; et al.
Favorite | TC[WOS]:24 TC[Scopus]:30  IF:4.6/5.6 | Submit date：2022/03/28
Clock And Data Recovery (Cdr)  Cmos  Distributed Driver  Four-level Pulse Amplitude (Pam-4)  Machâ Zehnder Modulator (Mzm)  Optical Digital-to-analog Converter (Dac)  Silicon Photonic (Siph)  Transmitter (Tx)  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
Jiang, Dongyang, Qi, Liang, Sin, Sai Weng, Maloberti, Franco, Martins, Rui P.. A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56(8), 2375-2387.
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:14  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS Conference paper
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui P. Martins. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS[C]:IEEE, 2019, 229-232.
Authors:  Xiaoteng Zhao;  Yong Chen;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:6 TC[Scopus]:7 | Submit date：2021/03/09
4-/8-level Pulse Amplitude Modulation (Pam-4/8)  Bang-bang Phase Detector (Bbpd)  Clock And Data Recovery (Cdr)  Half Rate  Non-return To Zero (Nrz)  Strongarm Comparator  Voltage-to-current (V/i) Converter  Xor