A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS

doi:10.1109/APCCAS47518.2019.8953158

UM > Faculty of Science and Technology > DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

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	A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS
	Xiaoteng Zhao 1; Yong Chen1 ; Pui-In Mak 1; Rui P. Martins1,2
	2019-11
Conference Name	15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019
Source Publication	Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption
Pages	229-232
Conference Date	11-14 November 2019
Conference Place	Bangkok, Thailand
Country	Thailand
Publisher	IEEE
Abstract	This paper reports a trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit featuring single-loop phase tracking, and low-power techniques at both the architecture and circuit levels to improve the overall energy efficiency. Fabricated in 28-nm CMOS, the prototype achieves a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s in NRZ/PAM-4/PAM-8 modes, respectively. The integrated jitter is <0.53 ps, and at least 1-UI jitter tolerance is achieved up to 10 MHz for all the three modes.
Keyword	4-/8-level Pulse Amplitude Modulation (Pam-4/8) Bang-bang Phase Detector (Bbpd) Clock And Data Recovery (Cdr) Half Rate Non-return To Zero (Nrz) Strongarm Comparator Voltage-to-current (V/i) Converter Xor
DOI	10.1109/APCCAS47518.2019.8953158
URL	View the original
Indexed By	CPCI-S
Language	英語English
WOS Research Area	Engineering
WOS Subject	Engineering, Electrical & Electronic
WOS ID	WOS:000530745700058
The Source to Article	https://ieeexplore.ieee.org/document/8953158
Scopus ID	2-s2.0-85078696897
Fulltext Access	View Full-Text via DOI View Full-Text via Web of Science View Full-Text via Scopus
Citation statistics
Document Type	Conference paper
Collection	DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS
Corresponding Author	Yong Chen
Affiliation	1.State Key Laboratory of Analog and Mixed-Signal VLSI and IME/FST-ECE, University of Macau, Macao, China 2.On leave from Instituto Superior Técnico, Universidade de Lisboa, Portugal
First Author Affilication	Faculty of Science and Technology
Corresponding Author Affilication	Faculty of Science and Technology
Recommended Citation GB/T 7714	Xiaoteng Zhao,Yong Chen,Pui-In Mak,et al. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS[C]:IEEE, 2019, 229-232.
APA	Xiaoteng Zhao., Yong Chen., Pui-In Mak., & Rui P. Martins (2019). A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS. Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption, 229-232.

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