English | 繁體

Search in the results

UM

Browse/Search Results:  1-10 of 10 Help

Selected(0)Clear Items/Page:    Sort:
An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R Journal article
Xu, Zixuan, Xing, Kai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R[J]. IEEE Journal of Solid-State Circuits, 2024, 59(3), 753-764.
Authors:  Xu, Zixuan;  Xing, Kai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/04/02
Ac-coupled Negative-r  Analog-to-digital Conversion (Adc)  Continuous-time Sigma-delta Modulator (Ct Sdm)  Noise-shaping Continuous Time Successive-approximation Register (Ns Ct-sar)  
A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA Journal article
Tan, Gaofeng, Qin, Xinyu, Liu, Yan, Guo, Mingqiang, Sin, Sai Weng, Wang, Guoxing, Lian, Yong, Qi, Liang. A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4781-4792.
Authors:  Tan, Gaofeng;  Qin, Xinyu;  Liu, Yan;  Guo, Mingqiang;  Sin, Sai Weng; et al.
Favorite | TC[WOS]:3 TC[Scopus]:4  IF:5.2/4.5 | Submit date：2024/02/23
0-x Mash  Analog-to-digital Converter (Adc)  Anti-aliasing Filtering  Continuous Time (Ct)  Maximum Stable Amplitude (Msa)  Multi-stage Noise Shaping (Mash)  
High-Performance Oversampling ADCs Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:181-218
Authors:  Chi-Hang Chan;  Yan Zhu;  Liang Qi;  Sai Weng Sin;  Maurits Ortmanns; et al.
Favorite | TC[Scopus]:0 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Cmos  Continuous-time Dsm (Ct Dsm)  Delta-sigma Modulator (Dsm)  Noise Shaping (Ns)  Oversampling  Pipeline Sar Adc  Successive Approximation Register (Sar)  
On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators Journal article
Jingying Zhang, Sai-Weng Sin, Yan Liu, Fan Ye, Guoxing Wang, Maurits Ortmanns, Liang Qi. On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 70(2), 356-360.
Authors:  Jingying Zhang;  Sai-Weng Sin;  Yan Liu;  Fan Ye;  Guoxing Wang; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.0/3.7 | Submit date：2023/01/30
Delta-sigma Modulator (Dsm)  Continuous-time (Ct)  Sturdy Multi-stage Noise-shaping (Smash)  Excess Loop Delay (Eld)  Loop-filter Connection  
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization Journal article
Wang,Wei, Chan,Chi Hang, Zhu,Yan, Martins,Rui P.. A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2020, 55(6), 1588-1598.
Authors:  Wang,Wei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:15  IF:4.6/5.6 | Submit date：2020/12/04
Analog-to-digital Conversion (Adc)  Continuous-time Delta-sigma Modulator (Ct-dsm)  Preliminary Sampling And Quantization (Psq) Technique  Single Amplifier Biquad (Sab)  Successiveapproximation-register (Sar) Architecture-based Quantizer (Qtz)  
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
Qi,Liang, Jain,Ankesh, Jiang,Dongyang, Sin,Sai Weng, Martins,Rui P., Ortmanns,Maurits. A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 344-355.
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.; et al.
Favorite | TC[WOS]:54 TC[Scopus]:48  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)  
A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
Qi, L., Jain, A., Jiang, D., Sin, S. W., Martins, R. P., Ortmanns, M.. A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 344-355.
Authors:  Qi, L.;  Jain, A.;  Jiang, D.;  Sin, S. W.;  Martins, R. P.; et al.
Favorite | TC[WOS]:54 TC[Scopus]:48  IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)  
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Δ\Σ Modulator with CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS Journal article
Wang,Wei, Zhu,Yan, Chan,Chi Hang, Martins,Rui Paulo. A 5.35-mW 10-MHz Single-Opamp Third-Order CT Δ\Σ Modulator with CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2018, 53(10), 2783-2794.
Authors:  Wang,Wei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui Paulo
Favorite | TC[WOS]:11 TC[Scopus]:13 | Submit date：2019/08/22
Analog-to-digital Conversion (Adc)  Continuous-time (Ct) Delta-sigma Modulator  Dac Driver  Passive Integrator  Single Amplifier Biquad (Sab)  
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Δ\Σ Modulator with CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS Journal article
Wang W., Zhu Y., Chan C.-H., Martins R.P.. A 5.35-mW 10-MHz Single-Opamp Third-Order CT Δ\Σ Modulator with CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2018, 53(10), 2783-2794.
Authors:  Wang W.;  Zhu Y.;  Chan C.-H.;  Martins R.P.
Favorite | TC[WOS]:11 TC[Scopus]:13 | Submit date：2019/02/11
Analog-to-digital Conversion (Adc)  Continuous-time (Ct) Delta-sigma Modulator  Dac Driver  Passive Integrator  Single Amplifier Biquad (Sab)  
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Delta Sigma Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS Conference paper
Wang, Wei, Zhu, Yan, Chan, Chi-Hang, Martins, Rui Paulo. A 5.35-mW 10-MHz Single-Opamp Third-Order CT Delta Sigma Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS[C], 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018, 2783-2794.
Authors:  Wang, Wei;  Zhu, Yan;  Chan, Chi-Hang;  Martins, Rui Paulo
Favorite | TC[WOS]:11 TC[Scopus]:13 | Submit date：2018/10/30
Terms-analog-to-digital Conversion (Adc)  Continuous-time (Ct) Delta-sigma Modulator  Dac Driver  Passive Integrator  Single Amplifier Biquad (Sab)