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CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization Journal article
Fu, Yuzhao, Li, Jixuan, Yu, Wei Han, Un, Ka Fai, Chan, Chi Hang, Zhu, Yan, Martins, Rui P., Mak, Pui In. CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization[J]. IEEE Transactions on Circuits and Systems I-Regular Papers, 2024, 71(11), 4996-5004.
Authors:  Fu, Yuzhao;  Li, Jixuan;  Yu, Wei Han;  Un, Ka Fai;  Chan, Chi Hang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/07/04
Capacitance Lookup Table (Clut)  Circuits  Common Information Model (Computing)  Compute-in-memory (Cim)  Energy Efficiency  High Energy Efficiency  In-memory Computing  Indexes  Nonuniform Quantization (Nuq)  Table Lookup  Thermometers  Weight Updating  
A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization Conference paper
Xin, Guoqiang, Tan, Fei, Li, Junde, Chen, Junren, Yu, Wei Han, Un, Ka Fai, Martins, Rui P., Mak, Pui In. A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 882-887.
Authors:  Xin, Guoqiang;  Tan, Fei;  Li, Junde;  Chen, Junren;  Yu, Wei Han; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/10/10
5t-sram  Analog Non-uniform Quantization (Anuq)  Computing-in-memory (Clm)  Machine Learning (Ml)  Matrix-vector Multiplication (Mvm)  Partial Sum Boosting (Psb)  
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation Conference paper
ZHANG RAN, UN KA FAI, GUO MINGQIANG, QI LIANG, XU DENGKE, ZHAO WEIBING, RUI P. MARTINS, FRANCO MALOBERTI, SIN SAI WENG. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  ZHANG RAN;  UN KA FAI;  GUO MINGQIANG;  QI LIANG;  XU DENGKE; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/08/19
Machine Learning  Edge Computation  Computing-in-memory  Delta-sigma Converter  Floating Inverter Amplifier  
Incendio: Priority-based Scheduling for Alleviating Cold Start in Serverless Computing Journal article
Cai, Xinquan, Sang, Qianlong, Hu, Chuang, Gong, Yili, Suo, Kun, Zhou, Xiaobo, Cheng, Dazhao. Incendio: Priority-based Scheduling for Alleviating Cold Start in Serverless Computing[J]. IEEE Transactions on Computers, 2024, 73(7), 1780-1794.
Authors:  Cai, Xinquan;  Sang, Qianlong;  Hu, Chuang;  Gong, Yili;  Suo, Kun; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:3.6/3.2 | Submit date：2024/05/16
Serverless Computing  Cold Start  Priority  Prediction  Scheduling  In-memory Computing  Distributed Systems  
A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC Conference paper
He, Pengyu, Zhao, Yuanzhe, Xie, Heng, Wang, Yang, Yin, Shouyi, Li, Li, Zhu, Yan, Martins, R. P., Chan, Chi Hang, Zhang, Minglei. A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  He, Pengyu;  Zhao, Yuanzhe;  Xie, Heng;  Wang, Yang;  Yin, Shouyi; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2 | Submit date：2024/06/05
Power Demand  In-memory Computing  Throughput  Energy Efficiency  Hardware  Common Information Model (Computing)  Artificial Intelligence  
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity Journal article
Wu, Hao, Chen, Yong, Yuan, Yiyang, Yue, Jinshan, Fu, Xiangqu, Ren, Qirui, Luo, Qing, Mak, Pui In, Wang, Xinghua, Zhang, Feng. A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, 71(2), 689-702.
Authors:  Wu, Hao;  Chen, Yong;  Yuan, Yiyang;  Yue, Jinshan;  Fu, Xiangqu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2024/02/22
Algebraic Sparsity (As)  Cmos  Computing-in-memory (Cim)  Multiply-accumulation (Mac)  Structured Sparsity (Ss)  Super-resolution (Sr)  Texture Sparsity (Ts)  
A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity Journal article
Wu, Hao, Chen, Yong, Yuan, Yiyang, Yue, Jinshan, Wang, Xinghua, Li, Xiaoran, Zhang, Feng. A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Wu, Hao;  Chen, Yong;  Yuan, Yiyang;  Yue, Jinshan;  Wang, Xinghua; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/07/04
Accuracy  Artificial Intelligence  Artificial Intelligence (Ai)  Circuits  Cmos  Computing-in-memory (Cim)  Energy Efficiency  Energy Efficiency  Look-up Table (Lut)  Multiply-accumulation (Mac)  Neural Network (Nn)  Power Demand  Radix16  Table Lookup  Throughput  Unstructured Sparsity  Winograd Convolution  
P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer Journal article
Fu, Xiangqu, Ren, Qirui, Wu, Hao, Xiang, Feibin, Luo, Qing, Yue, Jinshan, Chen, Yong, Zhang, Feng. P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4938-4948.
Authors:  Fu, Xiangqu;  Ren, Qirui;  Wu, Hao;  Xiang, Feibin;  Luo, Qing; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:5.2/4.5 | Submit date：2024/02/22
Accelerator  Cmos  Computing-in-memory (Cim)  Dynamic Prune  Prediction Network  Vision Transformer (Vit)  
A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory Conference paper
Wei-Han Yu, Massimo Giordano, Rohan Doshi, Minglei Zhang, Pui-In Mak, Rui P. Martins, Boris Murmann. A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory[C], 2021, 326-329.
Authors:  Wei-Han Yu;  Massimo Giordano;  Rohan Doshi;  Minglei Zhang;  Pui-In Mak; et al.
Favorite | TC[WOS]:8 TC[Scopus]:9 | Submit date：2021/10/28
Deep Neural Networks  Hardware Accelerators  In-memory Computing  Mixed-signal Integrated Circuits  Switched Capacitor Circuits