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A 310 nW 14.2-bit iterative-incremental ADC for wearable sensing systems Conference paper
Tan-Tan Zhang, Man-Kay Law, Bo Wang, Pui-In Mak, Mang-I Vai, Rui P. Martins. A 310 nW 14.2-bit iterative-incremental ADC for wearable sensing systems[C], 2018, 1-4.
Authors:  Tan-Tan Zhang;  Man-Kay Law;  Bo Wang;  Pui-In Mak;  Mang-I Vai; et al.
Favorite | TC[WOS]:3 TC[Scopus]:1 | Submit date：2019/02/11
Chopping  Dynamic Element Matching  Energy Efficiency  Incremental Adc  Sensor Interface  Two-step  Ultra-low-power  Vearable Sensing System  
A 2-μW 45-nV/√Hz Readout Front End with Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop Journal article
Jiangchao Wu, Man-Kay Law, Pui-In Mak, Rui P. Martins. A 2-μW 45-nV/√Hz Readout Front End with Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63(4), 351-355.
Authors:  Jiangchao Wu;  Man-Kay Law;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:42 TC[Scopus]:48 | Submit date：2019/02/11
Capacitively Coupled Instrumentation Amplifier (Ccia)  Dc Servo Loop (Dsl)  Multiple Chopping  Neural Recording Front End  Pseudofeedback Amplifier  Ripple Reduction Loop (Rrl)  
A 2 µW 45 nV/√Hz Readout Frontend With Multiple Chopping Active-High-Pass Ripple Reduction Loop and Pseudo-Feedback DC Servo Loop Journal article
Wu, J., Law, M. K., Mak, P. I., Martins, R. P.. A 2 µW 45 nV/√Hz Readout Frontend With Multiple Chopping Active-High-Pass Ripple Reduction Loop and Pseudo-Feedback DC Servo Loop[J]. IEEE Transactions on Circuits and Systems - II, 2016, 351-355.
Authors:  Wu, J.;  Law, M. K.;  Mak, P. I.;  Martins, R. P.
Favorite |   IF:4.0/3.7 | Submit date：2022/01/24
Capacitively coupled instrumentation amplifier (CCIA)  dc servo loop (DSL)  multiple chopping  neural recording front end  pseudofeedback amplifier  ripple reduction loop (RRL)  
Design of a Low-Power Low-Noise Bio-Potential Readout Front-End in CMOS Conference paper
Chon-Teng Ma, Pui-In Mak, Mang-I Vai, Peng-Un Mak, Sio-Hang Pun, R. P. Martins. Design of a Low-Power Low-Noise Bio-Potential Readout Front-End in CMOS[C], 2008.
Authors:  Chon-Teng Ma;  Pui-In Mak;  Mang-I Vai;  Peng-Un Mak;  Sio-Hang Pun; et al.
Favorite |  | Submit date：2019/03/13
Bio-potential Readout Front-end  Chopping Stabilization  Instrumentation Amplifier  Spike Tracking Clock