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A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Phase Locked Loops  Type-i  
7.4 A 0.027mm25.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrmsJitter and -74.2dBc Reference Spur Conference paper
Huang, Yunbo, Chen, Yong, Yang, Zunsong, Martins, Rui P., Mak, Pui In. 7.4 A 0.027mm25.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrmsJitter and -74.2dBc Reference Spur[C]:IEEE, 2024, 130-132.
Authors:  Huang, Yunbo;  Chen, Yong;  Yang, Zunsong;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[Scopus]:1 | Submit date：2024/05/16
A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur Conference paper
Chen, Tianle, Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Zheng, Xuqiang, Guo, Xuan, Iizuka, Tetsuya, Mak, Pui In, Chen, Yong, Li, Bo. A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Chen, Tianle;  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Meng, Xianghe; et al.
Favorite | TC[Scopus]:0 | Submit date：2024/10/10
Power-Efficient RF and mm-Wave VCOs/PLL Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:51-89
Authors:  Hao Guo;  Zunsong Yang;  Chee Cheow Lim;  Harikrishnan Ramiah;  Yatao Peng; et al.
Favorite | TC[Scopus]:0 | Submit date：2023/08/03
Harmonic Tuning  Inverse Class-f  Jitter  Millimeter Wave (mm-Wave)  Mode-switching  Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Subsampling  Voltage-controlled Oscillator (Vco)  
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM Journal article
Yang, Zunsong, Chen, Yong, Yuan, Jia, Mak, Pui In, Martins, Rui P.. A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 30(2), 238-242.
Authors:  Yang, Zunsong;  Chen, Yong;  Yuan, Jia;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:20 TC[Scopus]:21  IF:2.8/2.8 | Submit date：2022/03/04
Binary Frequency Shift Keying (Bfsk)  Frequency-locked Loop (Fll)  Integer-n  Phase Detector (Pd)  Phase Noise (Pn)  Phase-locked Loop (Pll)  Push-pull  Reference (Ref) Spur  Sub-sampling (Ss)  Voltage-controlled Oscillator (Vco)  
A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
Zunsong Yang, Yong Chen, Pui In Mak, Rui P. Martins. A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 68(6), 2307-2316.
Authors:  Zunsong Yang;  Yong Chen;  Pui In Mak;  Rui P. Martins
Favorite | TC[WOS]:13 TC[Scopus]:15  IF:5.2/4.5 | Submit date：2021/09/20
Cmos  Current-reuse Sampling Phase Detector (Crs-pd)  Integrated Jitter  Loop Filter (Lf)  Master-slave Sampling Filter (Mssf)  Master-slave Sampling Phase Detector (Mss-pd)  Phase Noise (Pn)  Phase-locked Loop (Pll)  Reference Spur  Ring Voltage-controlled Oscillator (Vco)  Type-i  Type-ii  
A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM Journal article
Yang,Zunsong, Chen,Yong, Mak,Pui In, Martins,Rui P.. A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM[J]. IEEE Solid-State Circuits Letters, 2020, 3, 494-497.
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:18 TC[Scopus]:19 | Submit date：2021/03/09
Cmos  In-band Phase Noise (Pn)  Narrow-pulse-sampling (Nps)  Phase-locked Loop (Pll)  Reference (Ref) Spur  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)  
A 0.003-mm2 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Conference paper
Yang,Zunsong, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.003-mm2 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS[C], 2020, 283-284.
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:7 | Submit date：2021/03/09
Phase Detector  Phase Locked Loop (Pll)  Reference Spur  Ring Voltage-controlled Oscillator (Vco)  Rms Jitter  
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
Yang,Zunsong, Chen,Yong, Yang,Shiheng, Mak,Pui In, Martins,Rui P.. A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector[J]. IEEE Access, 2019, 8, 2222-2232.
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:19 TC[Scopus]:20  IF:3.4/3.7 | Submit date：2021/03/09
Cmos  Dual Loop  Phase-locked Loop (Pll)  Frequency Detector (Fd)  Phase Detector (Pd)  Figure-of-merit (Fom)  Millimeter (Mm)-wave  Voltage-to-current Converter (Vic)  Voltage-controlled Oscillator (Vco)  Divider-by-4  Dynamic Latch  
A 6.5 ×7μ m2 0.98-to-1.5 mW Nonself-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4-44 GHz) Journal article
Chen,Yong, Yang,Zunsong, Zhao,Xiaoteng, Huang,Yunbo, Mak,Pui In, Martins,Rui P.. A 6.5 ×7μ m2 0.98-to-1.5 mW Nonself-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4-44 GHz)[J]. IEEE Solid-State Circuits Letters, 2019, 2(5), 37-40.
Authors:  Chen,Yong;  Yang,Zunsong;  Zhao,Xiaoteng;  Huang,Yunbo;  Mak,Pui In; et al.
Favorite | TC[WOS]:19 TC[Scopus]:23 | Submit date：2021/03/09
5g Bands  Current-mode-logic (Cml)  Figure-of-merit (Fom)  Frequency Divider  Locking Range (Lr)  Non-self-oscillation-mode (Nsom)  Phasor  Self-oscillation-mode (Som)