A dual-edge subsampling phase-locked loop (SSPLL) is proposed to reduce the in-band phase noise (PN) of the crystal oscillator (XO) and reference buffer (RBUF) by 3dB without degrading frequency resolution. It is able to achieve even and odd locking modes by configuring the dual-edge subsampling phase detector (SSPD) to ensure that the PLL can lock in steps of F. With a 100-MHz input reference and 6.5-to-6.9-GHz output, the prototype in 65-nm CMOS achieves an RMS jitter of 44fs, a jitter-power figure-of-merit (FOM) of -260.7-dB, and a spur level of -76.5dBc. The total power consumption is 4.4mW at 6.8GHz.