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E3 ubiquitin ligase UBR5 modulates circadian rhythm by facilitating the ubiquitination and degradation of the key clock transcription factor BMAL1 Journal article
Duan, Chunyan, Li, Yue, Zhi, Haoyu, Tian, Yao, Huang, Zhengyun, Chen, Suping, Zhang, Yang, Liu, Qing, Zhou, Liang, Jiang, Xiaogang, Ullah, Kifayat, Guo, Qing, Liu, Zhaohui, Xu, Ying, Han, Junhai, Hou, Jiajie, O’Connor, Darran P., Xu, Guo qiang. E3 ubiquitin ligase UBR5 modulates circadian rhythm by facilitating the ubiquitination and degradation of the key clock transcription factor BMAL1[J]. ACTA PHARMACOLOGICA SINICA, 2024, 45, 1793-1808.
Authors:  Duan, Chunyan;  Li, Yue;  Zhi, Haoyu;  Tian, Yao;  Huang, Zhengyun; et al.
Favorite | TC[WOS]:2 TC[Scopus]:1  IF:6.9/7.6 | Submit date：2024/06/05
Bmal1  Circadian Rhythm  Proteomics  Transcriptional Activity  Ubiquitination  Ubr5  
A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment Journal article
Li, Haoran, Xu, Tailong, Meng, Xi, Yin, Jun, Martins, Rui P., Mak, Pui In. A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Li, Haoran;  Xu, Tailong;  Meng, Xi;  Yin, Jun;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/10/10
Fast Locking  Frequency Synthesis  Frequency-locked Loop (Fll)  Low Jitter  Millimeter-wave (Mm-wave)  Phase-locked Loop (Pll)  Reference (Ref.) Spur  Sub-sampling Phase Detector (Sspd)  Voltage-controlled Oscillator (Vco)  
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation Conference paper
ZHANG RAN, UN KA FAI, GUO MINGQIANG, QI LIANG, XU DENGKE, ZHAO WEIBING, RUI P. MARTINS, FRANCO MALOBERTI, SIN SAI WENG. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C]:IEEE, 2024.
Authors:  ZHANG RAN;  UN KA FAI;  GUO MINGQIANG;  QI LIANG;  XU DENGKE; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/08/19
Machine Learning  Edge Computation  Computing-in-memory  Delta-sigma Converter  Floating Inverter Amplifier  
10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrmsJitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment Conference paper
Li, Haoran, Xu, Tailong, Meng, Xi, Yin, Jun, Martins, Rui P., Mak, Pui In. 10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrmsJitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment[C]:IEEE, 2024, 204-206.
Authors:  Li, Haoran;  Xu, Tailong;  Meng, Xi;  Yin, Jun;  Martins, Rui P.; et al.
Favorite | TC[Scopus]:4 | Submit date：2024/05/16
Fully Symmetrical Obfuscated Interconnection and Weak-PUF-Assisted Challenge Obfuscation Strong PUFs Against Machine-Learning Modeling Attacks Journal article
Xu, Chongyao, Zhang, Litao, Mak, Pui In, Martins, Rui P., Law, Man Kay. Fully Symmetrical Obfuscated Interconnection and Weak-PUF-Assisted Challenge Obfuscation Strong PUFs Against Machine-Learning Modeling Attacks[J]. IEEE Transactions on Information Forensics and Security, 2024, 19, 3927-3942.
Authors:  Xu, Chongyao;  Zhang, Litao;  Mak, Pui In;  Martins, Rui P.;  Law, Man Kay
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:6.3/7.3 | Submit date：2024/05/16
Physical Unclonable Function (Puf)  Machine Learning (Ml)  Modeling Attack  Symmetrical Obfuscated Interconnection (Soi)  Challenge Obfuscation  Reverse Engineering (Re)  
An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R Journal article
Xu, Zixuan, Xing, Kai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R[J]. IEEE Journal of Solid-State Circuits, 2024, 59(3), 753-764.
Authors:  Xu, Zixuan;  Xing, Kai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/04/02
Ac-coupled Negative-r  Analog-to-digital Conversion (Adc)  Continuous-time Sigma-delta Modulator (Ct Sdm)  Noise-shaping Continuous Time Successive-approximation Register (Ns Ct-sar)  
Absolute quantification of nucleic acid on digital microfluidics platform based on superhydrophobic–superhydrophilic micropatterning Journal article
Meng, Li, Li, Mingzhong, Xu, Zhenyu, Lv, Aman, Jia, Yanwei, Chen, Meiwan, Mak, Pui In, Martins, Rui P., Law, Man Kay. Absolute quantification of nucleic acid on digital microfluidics platform based on superhydrophobic–superhydrophilic micropatterning[J]. Sensors and Actuators B: Chemical, 2024, 402, 135079.
Authors:  Meng, Li;  Li, Mingzhong;  Xu, Zhenyu;  Lv, Aman;  Jia, Yanwei; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:8.0/7.0 | Submit date：2024/04/02
Digital Microfluidics  Dlamp  High-throughput  Super-wettability  
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation Conference paper
Zhang, Ran, Un, Ka Fai, Guo, Mingqiang, Qi, Liang, Xu, Dengke, Zhao, Weibing, Martins, R. P., Maloberti, Franco, Sin, Sai Weng. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C], 2024.
Authors:  Zhang, Ran;  Un, Ka Fai;  Guo, Mingqiang;  Qi, Liang;  Xu, Dengke; et al.
Favorite | TC[Scopus]:0 | Submit date：2024/08/05
Correction to: E3 ubiquitin ligase UBR5 modulates circadian rhythm by facilitating the ubiquitination and degradation of the key clock transcription factor BMAL1 (Acta Pharmacologica Sinica, (2024), 10.1038/s41401-024-01290-z) Other
2024-01-01
Authors:  Duan, Chun Yan;  Li, Yue;  Zhi, Hao Yu;  Tian, Yao;  Huang, Zheng Yun; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/07/04
A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS Conference paper
Yang, Jian, Xu, Tailong, Meng, Xi, Li, Zhenghao, Yin, Jun, Mak, Pui In, Martins, Rui P., Pan, Quan. A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  ; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/06/05