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A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur Conference paper
Chen, Tianle, Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Zheng, Xuqiang, Guo, Xuan, Iizuka, Tetsuya, Mak, Pui In, Chen, Yong, Li, Bo. A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Chen, Tianle;  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Meng, Xianghe; et al.
Favorite | TC[Scopus]:0 | Submit date：2024/10/10
Phase Noise  Power Demand  Laser Mode Locking  Prototypes  Detectors  Crystals  Very Large Scale Integration  
A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Power  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Type-i  
A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM Conference paper
Ren, Hongyu, Huang, Yunbo, Yang, Zunsong, Chen, Tianle, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Li, Zhongmao, Iizuka, Tetsuya, Mak, Pui In, Chen, Yong, Li, Bo. A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM[C]:IEEE Computer Society, 2024, 113-116.
Authors:  Ren, Hongyu;  Huang, Yunbo;  Yang, Zunsong;  Chen, Tianle;  Meng, Xianghe; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/12/05
Clock Generator  Frequency Synthesizer  Low Jitter  Low Power  Low Spur  Phase-locked Loop (Pll)  Reference Sampling  Type-ii