| Residential College | false |
| Status | 已發表Published |
| A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM | |
Ren, Hongyu1,2; Huang, Yunbo3 ; Yang, Zunsong1; Chen, Tianle1,2; Meng, Xianghe1; Yan, Weiwei1; Zhang, Weidong1; Li, Zhongmao1; Iizuka, Tetsuya4; Mak, Pui In3 ; Chen, Yong5; Li, Bo1
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| 2024 | |
| Conference Name | 50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024 |
| Source Publication | European Solid-State Circuits Conference
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| Pages | 113-116 |
| Conference Date | 9-12 September 2024 |
| Conference Place | Bruges |
| Country | Belgium |
| Publisher | IEEE Computer Society |
| Abstract | A type-II reference-sampling phase-locked loop (PLL) with a non-uniform octuple-sampling phase detector (PD) is proposed to lower the PD's in-band phase noise without raising the PLL's input load and crystal oscillator's power consumption. A low-noise multi-modulus divider and clock generator are utilized to generate sampling clocks without power-hungry retimers, further improving the jitter-power Figure-of-Merit (FOM). With a 150 − MHz input reference, the prototype in 28-nm CMOS achieves an RMS jitter of 55 fs and a FOM of - 259dB with a spur level of -91.9 dBc. The total power consumption is 3.34 mW at 4.8 GHz. |
| Keyword | Clock Generator Frequency Synthesizer Low Jitter Low Power Low Spur Phase-locked Loop (Pll) Reference Sampling Type-ii |
| DOI | 10.1109/ESSERC62670.2024.10719490 |
| URL | View the original |
| Language | 英語English |
| Scopus ID | 2-s2.0-85208422354 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Conference paper |
| Collection | THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
| Corresponding Author | Huang, Yunbo; Yang, Zunsong; Li, Bo |
| Affiliation | 1.Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China 2.University of Chinese Academy of Sciences, Beijing, China 3.University of Macau, Macao 4.The University of Tokyo, Tokyo, Japan 5.Tsinghua University, Beijing, China |
| Corresponding Author Affilication | University of Macau |
| Recommended Citation GB/T 7714 | Ren, Hongyu,Huang, Yunbo,Yang, Zunsong,et al. A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM[C]:IEEE Computer Society, 2024, 113-116. |
| APA | Ren, Hongyu., Huang, Yunbo., Yang, Zunsong., Chen, Tianle., Meng, Xianghe., Yan, Weiwei., Zhang, Weidong., Li, Zhongmao., Iizuka, Tetsuya., Mak, Pui In., Chen, Yong., & Li, Bo (2024). A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM. European Solid-State Circuits Conference, 113-116. |
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