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A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator Conference paper
Junhao Liang, Sai-Weng Sin, U. Seng-Pan, Franco Maloberti, R.P. Martins, Hanjun Jiang. A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator[C]:IEEE, 2019, 309-312.
Authors:  Junhao Liang;  Sai-Weng Sin;  U. Seng-Pan;  Franco Maloberti;  R.P. Martins; et al.
Favorite | TC[WOS]:4 TC[Scopus]:6 | Submit date：2021/03/09
Ct Sigma Delta Ad Converter  Ecg  High Impedance  Non-invertering Integrator  Programmable Integrator  
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
Xing D., Zhu Y., Chan C.-H., Maloberti F., Seng-Pan U., Martins R.P.. Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(2), 489-501.
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.; et al.
Favorite | TC[WOS]:2 TC[Scopus]:5  IF:5.2/4.5 | Submit date：2019/02/11
Reference Interference  Sar Adc  Time-interleaved Scheme  Two-step Sar Conversion  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
Liu J., Chan C.-H., Sin S.-W., Seng-Pan U., Martins R.P.. Accuracy-enhanced variance-based time-skew calibration using SAR as window detector[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(2), 481-485.
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:2.8/2.8 | Submit date：2019/02/13
Bandwidth Mismatches  Split-digital To Analog Converter (Dac)  Successive-approximation-register (Sar) Analog-to-digital Converter (Adc)  Time-interleaved (Ti)  Variance Based  Window Detector (Wd)  
A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA Journal article
Balan Z., Ramiah H., Rajendran J., Vitee N., Shasidharan P.N., Yin J., Mak P.-I., Martins R.P.. A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA[J]. Integration, 2019.
Authors:  Balan Z.;  Ramiah H.;  Rajendran J.;  Vitee N.;  Shasidharan P.N.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/02/11
Bluetooth Low Energy (Ble)  Cmos Receiver  Current-reuse  Forward Body Bias  I/q Mixers  Low Power  Quadrature Lna  Voltage-controlled Oscillator (Vco)  Zigbee  
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
Jiang W., Zhu Y., Chan C.-H., Murmann B., Seng-Pan U., Martins R.P.. A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler[C], 2018, 235-238.
Authors:  Jiang W.;  Zhu Y.;  Chan C.-H.;  Murmann B.;  Seng-Pan U.; et al.
Favorite | TC[WOS]:4 TC[Scopus]:5 | Submit date：2019/02/11
Background Calibration  Current Integrating Sampler  Time-interleaved Adc  Timing Skew  
An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H Conference paper
Zhu Y., Chan C.-H., Martins R.P.. An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H[C], 2018, 95-96.
Authors:  Zhu Y.;  Chan C.-H.;  Martins R.P.
Favorite | TC[Scopus]:1 | Submit date：2019/02/11
Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC Journal article
Wang G., Li C., Zhu Y., Zhong J., Lu Y., Chan C.-H., Martins R.P.. Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(11), 3707-3719.
Authors:  Wang G.;  Li C.;  Zhu Y.;  Zhong J.;  Lu Y.; et al.
Favorite | TC[WOS]:5 TC[Scopus]:5 | Submit date：2019/02/11
Bridge Dac  Gain Error Calibration  Low-dropout (Ldo) Regulator  Sar Adc  Testing Signal Generation  
A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
Zhu Y., Chan C.-H., Zheng Z.-H., Li C., Zhong J.-Y., Martins R.P.. A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(11), 3606-3616.
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.; et al.
Favorite | TC[WOS]:13 TC[Scopus]:14 | Submit date：2019/02/11
Passive Sharing  Pipelined-sar Adc  Sampling Front-end Design  Switch Bootstrap Technique  Time-interleaved Adc  
Nano-ampere low-dropout regulator designs for IoT devices Journal article
Huang Y., Lu Y., Maloberti F., Martins R.P.. Nano-ampere low-dropout regulator designs for IoT devices[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(11), 4017-4026.
Authors:  Huang Y.;  Lu Y.;  Maloberti F.;  Martins R.P.
Favorite | TC[WOS]:53 TC[Scopus]:64 | Submit date：2019/02/11
Dynamic Current Boosting  Ldo Regulator  Output-capacitor-free Ldo Regulator  Ultra-low Quiescent Ldo  
A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure Conference paper
Song Y., Zhu Y., Chan C.-H., Geng L., Martins R.P.. A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure[C], 2018, 203-204.
Authors:  Song Y.;  Zhu Y.;  Chan C.-H.;  Geng L.;  Martins R.P.
Favorite | TC[WOS]:4 TC[Scopus]:21 | Submit date：2019/02/11
Σδ Adc  Pipelined-sar Adc