This paper discusses design methodologies for high-speed SAR ADCs. A comparison of various architectures and the study of benefits and limits identify the best solution for high-speed and medium resolution. It is an interleaving architecture with the channel implemented by a fast coarse SAR quantizer and 2-way time-interleaved (TI) fine SAR ADCs. We propose a float-then-write code transfer technique for optimizing the transfer sequence and reducing the reference interference. Furthermore, we also study and compare the output impedance of the reference generation as well as the reference interference for the optimized code transfer scheme and the conventional bit-by-bit in both single-channel and TI scenarios. In addition, the mismatches in TI channels and two sub-ADCs are discussed. A 10-bit test vehicle fabricated in 65-nm CMOS confirms experimentally the proposed methods operating with 1.2-V supply at 700 MS/s. The circuit occupies an active area of 0.084 mm and achieves a signal-to-noise and distortion ratio at a Nyquist of 53.3 dB, with a power consumption of 9.5 mW. The Walden figure-of-merit is 36 fJ/conversion-step.