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Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections with <0.83% Bit-Error Rate Conference paper
Xu, Chongyao, Zhang, Jieyun, Law, Man-Kay, Jiang, Yang, Zhao, Xiaojin, Mak, Pui-ln, Martins, Rui P.. Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections with <0.83% Bit-Error Rate[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021.
Authors:  Xu, Chongyao;  Zhang, Jieyun;  Law, Man-Kay;  Jiang, Yang;  Zhao, Xiaojin; et al.
Favorite | TC[WOS]:4 TC[Scopus]:5 | Submit date：2022/08/21
Auto-Calibration Technique for Current-Based Bandgap Voltage Reference [Highlighted Paper] Conference paper
U, Chi Wa, Law, Man-Kay, Lam, Chi-Seng, Martins, Rui P.. Auto-Calibration Technique for Current-Based Bandgap Voltage Reference [Highlighted Paper][C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021.
Authors:  U, Chi Wa;  Law, Man-Kay;  Lam, Chi-Seng;  Martins, Rui P.
Favorite | TC[WOS]:0 TC[Scopus]:3 | Submit date：2022/08/09
A 15.2-To-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-To-188.1dBc/Hz FoM in 28nm CMOS Conference paper
Meng, Xi, Guo, Junqi, Li, Haoran, Yin, Jun, Mak, Pui In, Martins, Rui P.. A 15.2-To-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-To-188.1dBc/Hz FoM in 28nm CMOS[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021.
Authors:  Meng, Xi;  Guo, Junqi;  Li, Haoran;  Yin, Jun;  Mak, Pui In; et al.
Favorite | TC[WOS]:3 TC[Scopus]:9 | Submit date：2022/05/13
An Arithmetic Progression Switched-Capacitor DC-DC Converter with Soft VCR Transitions Achieving 93.7% Peak Efficiency and 400 mA Output Current Conference paper
Jiang, Yang, Law, Man-Kay, Mak, Pui-In, Martins, Rui P.. An Arithmetic Progression Switched-Capacitor DC-DC Converter with Soft VCR Transitions Achieving 93.7% Peak Efficiency and 400 mA Output Current[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021.
Authors:  Jiang, Yang;  Law, Man-Kay;  Mak, Pui-In;  Martins, Rui P.
Favorite | TC[WOS]:2 TC[Scopus]:4 | Submit date：2022/08/21
Dc-dc Power Converters  Topology  
A 0.46pJ/bit Ultralow-Power Entropy-Preselection-Based Strong PUF with Worst-Case BER<6.7×10-6 Conference paper
Liu, Jiahao, Zhu, Yan, Chan, Chi Hang, Martins, Rui Paulo. A 0.46pJ/bit Ultralow-Power Entropy-Preselection-Based Strong PUF with Worst-Case BER<6.7×10-6[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021.
Authors:  Liu, Jiahao;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui Paulo
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2022/05/13
A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancemen Conference paper
Li, J., Chen, J., Un, K. F., Yu, W. H., Mak, P. I., Martins, R. P.. A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancemen[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021.
Authors:  Li, J.;  Chen, J.;  Un, K. F.;  Yu, W. H.;  Mak, P. I.; et al.
Favorite | TC[WOS]:2  | Submit date：2022/01/25
Computation Efficiency  Convolutional Neural Network (Cnn)  Fpga  Object Recognition  Reconfigurability  
A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement Conference paper
Li, Jixuan, Chen, Jiabao, Un, Ka Fai, Yu, Wei Han, Mak, Pui In, Martins, Rui P.. A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021.
Authors:  Li, Jixuan;  Chen, Jiabao;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In; et al.
Favorite | TC[WOS]:2 TC[Scopus]:5 | Submit date：2023/03/30
Computation Efficiency  Convolutional Neural Network (Cnn)  Fpga  Object Recognition  Reconfigurability  
A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process Conference paper
Zhang, Jincheng, Wu, Tianxiang, Chen, Yong, Ren, Junyan, Ma, Shunli. A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021.
Authors:  Zhang, Jincheng;  Wu, Tianxiang;  Chen, Yong;  Ren, Junyan;  Ma, Shunli
Favorite | TC[WOS]:0 TC[Scopus]:3 | Submit date：2022/05/13