Dynamic source adaptation and supply modulation can benefit the power efficiency and system functionality of energy-harvesting interfaces, voltage-scalable SoCs, device drivers, power amplifiers, and others. A switched-capacitor (SC) DC-DC converter can achieve high power conversion efficiency (PCE) and power density at the hundreds-of-mW. Several reconfigurable SC topologies emerged to generate multiple voltage conversion ratios (VCRs) systematically with lower conduction and parasitic losses in steady state [1]–[4]. However, during VCR transitions, the voltage imbalance among the flying capacitors (C FLY ) can induce charge redistribution loss. This hard-VCR-transition loss inevitably hurts the overall efficiency and remains unresolved. This work proposes an arithmetic progression (AP) SC DC-DC converter topology for systematic rational VCR generation while featuring soft VCR transitions. It demonstrates fixed voltages with each C FLY irrespective of VCR change to eliminate the C FLY voltage rebalance effect. The proposed AP topology also achieves theoretical optimum in terms of the steady-state slow-/fast switching-limited losses. Due to the inherent property of two-phase quasi-symmetric output charge (Q OUT ) delivery, it ensures a low output ripple without using a conventional dual-branch converter architecture. We further propose a cross-coupled bootstrapping (XCBS) gate driver, operating at half of switching frequency (f SW/2 ), to control the flying power switches adaptively. Realizing step-down VCRs of 5:4/3/2/1, the proposed AP converter reaches a measured peak PCE of 93.7% and a maximum output current of 400 mA. Featuring soft VCR transitions, it demonstrates an average PCE of up to 89% under a periodic VCR transition (f VCR_tran) at 100 kHz.