| Residential College | false |
| Status | 已發表Published |
| A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancemen | |
Li, J.1 ; Chen, J.1; Un, K. F.1 ; Yu, W. H.1; Mak, P. I.1; Martins, R. P.1,2
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| 2021-07-30 | |
| Conference Name | 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
| Source Publication | Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference
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| Conference Date | 07-10 November 2021 |
| Conference Place | Busan |
| Country | SOUTH KOREA |
| Publication Place | IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA |
| Publisher | IEEE |
| Abstract | A FPGA-based MobileNetV2 accelerator scores an energy efficiency of 50.4 GOPs/W in a Xlinix VC709 evaluation board. It innovates a double-layer multiply-accumulate (DLM) scheme with dynamic DSP allocation, resulting in 41.3% reduction of the memory access for the feature maps, while sustaining the occupation rate of the DSPs. A double-operation DSP technique also enhances the efficiency of the DSP for computing low precision fixed-point operations, which achieves a DSP efficiency of 0.73 GOPs/DSP for a 200MHz clock. |
| Keyword | Computation Efficiency Convolutional Neural Network (Cnn) Fpga Object Recognition Reconfigurability |
| URL | View the original |
| Indexed By | CPCI-S |
| Language | 英語English |
| WOS Research Area | Engineering |
| WOS Subject | Engineering, Electrical & Electronic |
| WOS ID | WOS:000768220800102 |
| The Source to Article | PB_Publication |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Conference paper |
| Collection | University of Macau |
| Corresponding Author | Un, K. F. |
| Affiliation | 1.University of Macau, Macau, China 2.Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal |
| First Author Affilication | University of Macau |
| Corresponding Author Affilication | University of Macau |
| Recommended Citation GB/T 7714 | Li, J.,Chen, J.,Un, K. F.,et al. A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancemen[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021. |
| APA | Li, J.., Chen, J.., Un, K. F.., Yu, W. H.., Mak, P. I.., & Martins, R. P. (2021). A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancemen. Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference. |
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