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A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur Conference paper
Chen, Tianle, Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Zheng, Xuqiang, Guo, Xuan, Iizuka, Tetsuya, Mak, Pui In, Chen, Yong, Li, Bo. A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Chen, Tianle;  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Meng, Xianghe; et al.
Favorite | TC[Scopus]:0 | Submit date：2024/10/10
Phase Noise  Power Demand  Laser Mode Locking  Prototypes  Detectors  Crystals  Very Large Scale Integration  
A Fully Integrated 48-V GaN Driver Using Parallel-Multistep-Series Reconfigurable Switched-Capacitor Bank Achieving 7.7nC/mm2 On-Chip Bootstrap Driving Density Conference paper
Xuchu Mu, Yang Jiang, Rui Martins, Pui-In Mak. A Fully Integrated 48-V GaN Driver Using Parallel-Multistep-Series Reconfigurable Switched-Capacitor Bank Achieving 7.7nC/mm2 On-Chip Bootstrap Driving Density[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Xuchu Mu;  Yang Jiang;  Rui Martins;  Pui-In Mak
Favorite | TC[Scopus]:0 | Submit date：2024/08/29
Switching Frequency  Prototypes  Switches  Logic Gates  Very Large Scale Integration  Capacitance  System-on-chip  
A 0.05-to-3.1A 585mA/mm3 97.3%-Efficiency Outphase Switched-Capacitor Hybrid Buck Converter with Relieved Capacitor Inrush Current and COUT-Free Operation Conference paper
Xiongjie Zhang, Qiaobo Ma, Anyang Zhao, Yang Jiang, Man-Kay Law, Pui-In Mak, Rui Martins. A 0.05-to-3.1A 585mA/mm3 97.3%-Efficiency Outphase Switched-Capacitor Hybrid Buck Converter with Relieved Capacitor Inrush Current and COUT-Free Operation[C]:Institute of Electrical and Electronics Engineers Inc., 2023.
Authors:  Xiongjie Zhang;  Qiaobo Ma;  Anyang Zhao;  Yang Jiang;  Man-Kay Law; et al.
Favorite | TC[Scopus]:0 | Submit date：2023/08/22
A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors Conference paper
Zhang, Minglei, Cao, Yuefeng, Zhu, Yan, Chan, Chi-Hang, Martins, R. P.. A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors[C]:Institute of Electrical and Electronics Engineers Inc., 2023.
Authors:  Zhang, Minglei;  Cao, Yuefeng;  Zhu, Yan;  Chan, Chi-Hang;  Martins, R. P.
Favorite | TC[Scopus]:5 | Submit date：2023/07/12
Dynamic Amplifier  Residue Amplifier  Pipelined-sar Adc  Linearization Technique  Bypass Capacitor  
A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS Conference paper
Zhang, Zhao, Zhang, Zhaoyu, Chen, Yong, Qi, Nan, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS[C]:Institute of Electrical and Electronics Engineers Inc., 2023.
Authors:  Zhang, Zhao;  Zhang, Zhaoyu;  Chen, Yong;  Qi, Nan;  Liu, Jian; et al.
Favorite | TC[Scopus]:1 | Submit date：2024/02/23